The updated list of publications is available at:

• Google Scholar
• Research Gate

Refereed Journal (SCI/SCIE Indexed):

1. Gadi Harshavardhan, B. V. Chandan, Kaushal Nigam and A. Tanveer, "Machine Learning Based Design and Optimization of Charge-Induced Hetero-Gate Tunnel FET for Low-Power Applications," Integration, Elsevier, pp. 1-11, Jul. 2026, (Accepted)

2. B. V. Chandan, Kaushal Nigam and A. Tanveer, “Design and Reliability Assessment of a Reconfigurable Tunneling Device for Ultra Low-Power Applications,” IEEE Transactions on Device and Materials Reliability, pp. 1-7, Jun. 2026, (Accepted), Early Access, https://doi.org/10.1109/TDMR.2026.3708312. 

3. H. Kumar, A. Patle, Kaushal Nigam, and C. Sahu, “GaSb/Si Heterojunction Segmented Channel Vertical TFET for High Sensitivity Gas Sensing in Biomedical and Industrial Environments," Applied Physics A, vol. 132, no. 597, Jun. 2026. https://doi.org/10.1007/s00339-026-09790-x.
4. H. Kumar, Kaushal Nigam, C. Sahu, and B.V. Chandan, “A Dielectric-Modulated Dual-Material Gate MOS-HEMT for Ultra-High Sensitivity Label-Free Biosensor," IEEE Transactions on Dielectrics and Electrical Insulation, pp. 1-8, May 2026. (Accepted), Early Access, https://doi.org/10.1109/TDEI.2026.3698812.   
5. Dharmender, Kaushal Nigam, Sanjana Bharath, Arpit Chaudhary, Sakshi Chaudhary, “Performance Optimization of Lead Free Rb2LiGaBr6-Cs2AgBil6 Double Absorber Perovskite Solar Cell using SCAPS-1D,” Modelling and Simulation in Materials Science and Engineering, pp. 1-13, May 2026. (Accepted), https://iopscience.iop.org/article/10.1088/1361-651X/ae8043/meta.
6. M. Sharma, Dharmender, S. Singh, S. Soni, Kaushal Nigam, and Piyush Yadav, “Numerical Insights into RbGeI3-CsSnGeI3 Dual-Absorber Perovskite Solar Cell with Optimized Transport Layers,” Journal of Materials Science, vol. 37, no. 13, pp. 1-19, Apr. 2026. https://doi.org/10.1007/s10854-026-17344-3. 
7. M. Bind, S. V. Singh, and Kaushal Nigam, “Hydrogen Gas (H₂) sensor based on GaAs/GaSb heterojunction charge plasma TFET: A simulation study,” Microsystem Technologies, vol. 32, pp. 1-21, Feb. 2026. https://doi.org/10.1007/s00542-026-06036-x.
8. P. Kwatra, S. V. Singh, Kaushal Nigam, and M. K. Bind, “Design and performance investigation of heterojunction electrically doped junctionless TFET for label-free biomolecule detection considering ambipolar conduction,” Micro and Nanostructures, vol. 211, no. 208564, Jan. 2026, doi: https://doi.org/10.1016/j.micrna.2026.208564.
9. B. V. Chandan, Kaushal Nigam, B. Acharya, and A. Tanveer, “Theoretical performance and reliability optimization of graphene based electrically doped tunnel FET under interface trap charge constraints: A device-level approach,” Microelectronics Reliability, vol. 175, Art. no. 115928, Oct. 2025, doi: https://doi.org/10.1016/j.microrel.2025.115928.
10. P. Gupta, S. S. Chauhan, Kaushal Nigam, D. Kumar, J. Madan, and R. Devlal, “Optimized dual absorber architecture for enhanced efficiency and stability in all-inorganic perovskite solar cells,” Multiscale and Multidisciplinary Modeling, Experiments and Design, vol. 8, p. 433, Aug. 2025, doi: https://doi.org/10.1007/s41939-025-01024-6.
11. P. Kwatra, S. V. Singh, and Kaushal Nigam, “Design and performance analysis of new metal strip incorporated dual oxide dual tunnel FET evaluating trap charges for augmented reliability,” Silicon, vol. 17, pp. 3897–3916, Sep. 2025, doi: https://doi.org/10.1007/s12633-025-03453-x.
12. A. Tanveer, Kaushal Nigam, and B. V. Chandan, “Numerical analysis and parametric optimization of multi-absorber layer all-inorganic perovskite solar cells employing double perovskites,” Modelling and Simulation in Materials Science and Engineering, vol. 33, Art. no. 075008, Sep. 2025, doi: https://doi.org/10.1088/1361-651X/ae0b9b.
13. B. V. Chandan and Kaushal Nigam, “Impact of interface trap densities on Mg₂Si-based electrostatically doped tunnel FET,” Modelling and Simulation in Materials Science and Engineering, vol. 33, Art. no. 075012, Sep. 2025, doi: https://doi.org/10.1088/1361-651X/ae0daa.
14. B. V. Chandan and Kaushal Nigam, “Insights into the effects of interface trap charges on electrostatic-based magnesium silicide tunneling interface,” IEEE Transactions on Device and Materials Reliability, vol. 25, pp. 921–933, Oct. 2025, https://ieeexplore.ieee.org/abstract/document/11204364.
15. D. Kumar, Kaushal Nigam, N. R. Kampelli, and P. Yadav, “Performance investigation of Z-shaped gate dielectric modulated electrically doped junctionless TFET based biosensor for biomedical application,” Micro and Nanostructures, vol. 208, Art. no. 208373, Oct. 2025, doi: https://doi.org/10.1016/j.micrna.2025.208373.
16. A. Patle, Kaushal Nigam, and C. Sahu, “Temperature investigation of step-T-shaped channel tunnel field-effect transistor biosensor for high sensitivity,” Measurement, vol. 257, Art. no. 118750, Aug. 2025, doi: https://doi.org/10.1016/j.measurement.2025.118750.
17. A. Kumar, N. Gupta, A. Jain, R. Gupta, K. Kumar, Kaushal Nigam, and A. K. Goyal, “Advanced perspectives on chalcogenide perovskite solar cells using CZTS as HTL for optimum efficiency,” Journal of Physics and Chemistry of Solids, vol. 208, Art. no. 113101, Aug. 2025, doi: https://doi.org/10.1016/j.jpcs.2025.113101.
18. P. Gupta, S. S. Chauhan, Kaushal Nigam, D. Kumar, and R. Devlal, “A comprehensive study on ETL and HTL layer optimization for the design and simulation of high-efficiency, stable lead-free CsSn₀.₅Ge₀.₅I₃ perovskite solar cells,” Multiscale and Multidisciplinary Modeling, Experiments and Design, vol. 8, p. 339, May 2025, doi: https://doi.org/10.1007/s41939-025-00926-9.
19. S. V. Singh, M. K. Bind, and Kaushal Nigam, “Work function engineered polarity-controlled TFET for digital circuit applications: Design and performance analysis,” Analog Integrated Circuits and Signal Processing, vol. 124, p. 41, Jun. 2025, doi: https://doi.org/10.1007/s10470-025-02446-5.
20. C. Rajan, A. R. Babhulkar, K. Nakhathe, M. Panchore, and Kaushal Nigam, “A hybrid machine learning model to predict reconfigurable field-effect transistor characteristics with limited dataset,” Semiconductor Science and Technology, vol. 10, Art. no. 075011, Jun. 2025, doi: https://doi.org/10.1088/1361-6641/ade7f3.
21. P. Kwatra, V. A. Tikkiwal, S. V. Singh, and K. Nigam, “Design and investigation of novel heterojunction stacked oxide-dual tunnelling FET assessing interface traps for improved reliability,” Physica Scripta, vol. 100, Art. no. 065019, May 2025, doi: https://doi.org/10.1088/1402-4896/add628.
22. Dharmender, K. K. Nigam, P. Yadav, S. Kuksal, T. Parashar, and S. S. Chauhan, “Numerical investigation of RbGeI₃-based lead-free perovskite solar cell with various Cu-based hole transport layers using SCAPS-1D,” Journal of Electronic Materials, vol. 54, pp. 2747–2766, Feb. 2025, doi: https://doi.org/10.1007/s11664-025-11740-x.
23. B. V. Chandan, K. K. Nigam, and A. Tanveer, “Performance and reliability investigation of Mg₂Si based tunnel FET under temperature variations for high-sensitivity applications,” Micro and Nanostructures, vol. 200, Art. no. 208084, Jan. 2025, doi: https://doi.org/10.1016/j.micrna.2025.208084.
24. B. V. Chandan and K. Nigam, “Performance and reliability of N-type doping-free TFETs: The role of compound semiconductor materials,” Multiscale and Multidisciplinary Modeling, Experiments and Design, vol. 8, p. 198, Jan. 2025, doi: https://doi.org/10.1007/s41939-025-00769-4.
25. M. K. Bind, K. Nigam, and S. V. Singh, “GaAs/Ge polarity controlled TFET biosensor for SARS-CoV-2 detection: A simulation-based study,” Microsystem Technologies, vol. 31, pp. 2067–2083, Dec. 2024, doi: https://doi.org/10.1007/s00542-024-05836-3.
26. M. K. Bind, K. Nigam, and S. V. Singh, “Design and performance evaluation of a heterojunction GaAs/GaSb PC-TFET for label-free biosensing applications,” Journal of Electronic Materials, vol. 54, pp. 1691–1708, Dec. 2024, doi: https://doi.org/10.1007/s11664-024-11643-3.
27. B. V. Chandan, M. P. Bakshi, and K. Nigam, “Reliability optimization of dopant-free TFET performance through advanced metal layer techniques,” Microelectronics Reliability, vol. 163, Art. no. 115542, Oct. 2024, doi: https://doi.org/10.1016/j.microrel.2024.115542.
28. M. K. Bind, S. V. Singh, and K. Nigam, “Design and performance analysis of polarity control junctionless TFET (PC-JL-TFET)-based biosensor,” Journal of Circuits, Systems and Computers, vol. 33, Art. no. 2450302, Jun. 2024, doi: https://doi.org/10.1142/S021812662450302X.
29. M. Shreyanshi, Sangeedh, K. Nigam, A. S. Raghuvanshi, and Dharmender, “Mole fraction-based approach for sensitivity analysis of dual material control gate polarity controlled tunnel field effect transistor for applications in biomedical engineering,” Journal of Circuits, Systems and Computers, vol. 33, Art. no. 2450206, Jan. 2024, doi: https://doi.org/10.1142/S0218126624502062.
30. B. V. Chandan, Dharmender, and K. Nigam, “A theoretical performance and reliability investigation of a vertical hetero oxide based JL-TFET under ideal conditions,” Silicon, vol. 16, pp. 4397–4413, Apr. 2024, doi: https://doi.org/10.1007/s12633-024-03010-y.
31. Dharmender, K. Nigam, P. Yadav, and V. A. Tikkiwal, “Performance analysis of dual material control gate cavity on source electrically doped TFET biosensor for biomedical applications,” Micro and Nanostructures, vol. 191, Art. no. 207844, Apr. 2024, doi: https://doi.org/10.1016/j.micrna.2024.207844.
32. M. K. Bind and K. Nigam, “Sensitivity and non-ideal issues analysis of a dielectric-modulated electrically doped junctionless TFET-based label-free biosensor,” IEEE Sensors Journal, vol. 24, pp. 24023–24030, Jun. 2024, https://ieeexplore.ieee.org/document/10565779.
33. B. V. Chandan and K. Nigam, “Theoretical and simulation-based assessment of electrically doped junctionless TFET with metal-strip and hetero-material considering interface trap charges,” Microelectronics Reliability, vol. 157, Art. no. 115393, Apr. 2024, doi: https://doi.org/10.1016/j.microrel.2024.115393.
34. Dharmender, K. Nigam, P. Yadav, and A. Kumar, “Investigation of Si₁−xGeₓ source dual material stacked gate oxide pocket doped hetero-junction TFET for low power and RF applications,”International Journal of Electronics, vol. 111, pp. 599–615, Jan. 2023, doi: https://doi.org/10.1080/00207217.2023.2173804.
35. K. Nigam and Dharmender, “A theoretical investigation of mole fraction-based N-pocket doped stack oxide TFET considering ideal conditions for reliability issues,” Microelectronics Reliability, vol. 155, Art. no. 115357, Feb. 2024, doi: https://doi.org/10.1016/j.microrel.2024.115357.
36. K. Nigam, Dharmender, V. A. Tikkiwal, and M. K. Bind, “Theoretical investigation of dual-material stacked gate oxide-source dielectric pocket TFET based on interface trap charges and temperature variations,” Journal of Circuits, Systems and Computers, vol. 32, Art. no. 2350252, Oct. 2023, doi: https://doi.org/10.1142/S0218126623502523.
37. M. K. Bind, S. V. Singh, and K. Nigam, “Design and investigation of the DM-PC-TFET-based biosensor for breast cancer cell detection,” Transactions on Electrical and Electronic Materials, vol. 24, pp. 381–395, May 2023, doi: https://doi.org/10.1007/s42341-023-00453-9.
38. P. Kwatra, K. Nigam, and S. V. Singh, “Design and analysis of novel bilateral tunnelling based tunnel FET considering workfunction engineered metal strip for enhanced performance,” Microelectronics Journal, vol. 139, Art. no. 105878, Jun. 2023, doi: https://doi.org/10.1016/j.mejo.2023.105878.
39. M. K. Bind, K. Nigam, and S. V. Singh, “Sensitivity assessment of electrically doped cavity on source junctionless tunnel field-effect transistor-based biosensor,” Journal of Circuits, Systems and Computers, vol. 32, Art. no. 2350018, Jan. 2023, doi: https://doi.org/10.1142/S0218126623500184.
40. P. Kwatra, K. Nigam, and S. V. Singh, “Design and performance evaluation of a novel dual tunneling based TFET considering trap charges for reliability improvement,” Silicon, vol. 15, no. 5, pp. 2407–2425, Oct. 2022, https://doi.org/10.1007/s12633-022-02188-3
41. P. Kwatra, K. Nigam, and S. V. Singh, “Performance investigation and impact of trap charges on novel lateral dual gate oxide-bilateral tunnelling based field effect transistor,” Microelectronics Reliability, vol. 140, Art. no. 114872, Nov. 2022, doi: https://doi.org/10.1016/j.microrel.2022.114872.
42. P. Verma, K. Nigam, and S. Kumar, “Impact of gate overlap and underlap on analog/RF and linearity performance of dual-material gate-oxide-stack double-gate TFET,” Applied Physics A, vol. 128, Art. no. 955, Sep. 2022, doi: https://doi.org/10.1007/s00339-022-06083-x.
43. Dharmender, K. Nigam, and S. Kumar, “Performance assessment of cavity on source dual material split gate GaAs/InAs/Ge junctionless TFET for label-free detection of biomolecules,” Applied Physics A, vol. 128, Art. no. 943, Aug. 2022, doi: https://doi.org/10.1007/s00339-022-06017-7.
44. K. Nigam, S. Kumar, and Dharmender, “Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET,” Journal of Computational Electronics, vol. 21, pp. 802–813, Apr. 2022, doi: https://doi.org/10.1007/s10825-022-01902-z.
45. M. K. Bind and K. Nigam, “Sensitivity analysis of junction-free electrostatically doped tunnel-FET based biosensor,” Silicon, vol. 14, pp. 7755–7767, Oct. 2021, doi: https://doi.org/10.1007/s12633-021-01444-2.
46. K. Nigam, P. Kwatra, and S. V. Singh, “Investigation and design of stacked oxide polarity gate JLTFET in the presence of interface trap charges for analog/RF applications,” Silicon, vol. 14, pp. 3963–3980, May 2021, doi: https://doi.org/10.1007/s12633-021-01162-9.
47. K. Nigam, P. N. Kondekar, B. V. Chandan, S. Kumar, V. A. Tikkiwal, Dharmender, K. S. Singh, E. Bhardwaj, S. Choubey, and S. Chaturvedi, “Performance and analysis of stack junctionless tunnel field effect transistor,” Silicon, vol. 14, pp. 1549–1558, Jan. 2021, doi: https://doi.org/10.1007/s12633-021-00958-z.
48. S. Kumar, K. Nigam, S. Chaturvedi, A. Inshad Khan, and A. Jain, “Performance improvement of double-gate TFET using metal strip technique,” Silicon, vol. 14, pp. 1759–1766, Jan. 2021, doi: https://doi.org/10.1007/s12633-021-00982-z.
49. K. M. S. Singh, S. Kumar, and K. Nigam, “Design and investigation of dielectrically modulated dual-material gate-oxide-stack double-gate TFET for label-free detection of biomolecules,” IEEE Transactions on Electron Devices, vol. 68, pp. 5784–5791, Sep. 2021, https://ieeexplore.ieee.org/document/9548324.
50. Nithyanshi, T. Mathur, V. A. Tikkiwal, and K. Nigam, “Feasibility analysis of a solar-assisted electric vehicle charging station model considering differential pricing,” Energy Storage, vol. 3, Art. no. e237, Mar. 2021, doi: https://doi.org/10.1002/est2.237.
51. S. Kumar, K. S. Singh, K. Nigam, and S. Chaturvedi, “Ambipolarity suppressed dual-material double-source T-shaped tunnel field-effect transistor,” Silicon, vol. 13, pp. 2065–2070, Jul. 2020, doi: https://doi.org/10.1007/s12633-020-00601-3.
52. Dharmender and K. Nigam, “Low-k dielectric pocket and workfunction engineering for DC and analog/RF performance improvement in dual material stack gate oxide double gate TFET,” Silicon, vol. 13, pp. 2347–2356, Nov. 2020, doi: https://doi.org/10.1007/s12633-020-00822-6.
53. K. Nigam, S. Kumar, K. S. Singh, E. Bhardwaj, S. Choubey, and S. Chaturvedi, “Temperature sensitivity analysis of SGO metal strip JL TFET,” IET Circuits, Devices & Systems, vol. 14, pp. 444–449, Mar. 2020, doi: https://doi.org/10.1049/iet-cds.2019.0412.
54. K. M. S. Singh, S. Kumar, and K. Nigam, “Impact of interface trap charges on analog/RF and linearity performances of dual-material gate-oxide-stack double-gate TFET,” IEEE Transactions on Device and Materials Reliability, vol. 20, pp. 404–412, Mar. 2020, https://ieeexplore.ieee.org/document/9055435.
55.  B. V. Chandan, C. Rajan, K. Nigam, and D. Sharma, “A fair comparison of the performance of charge plasma and electrostatic tunnel FETs for low-power high-frequency applications,” Journal of Computational Electronics, vol. 18, pp. 1201–1206, Aug. 2019, doi: https://doi.org/10.1007/s10825-019-01388-2.
56. E. Bhardwaj, K. Nigam, S. Choubey, and S. Chaturvedi, “Effect of ITCs on gate stacked JL-TFET based on work-function engineering,” IET Micro & Nano Letters, vol. 14, pp. 1238–1243, Oct. 2019, doi: https://doi.org/10.1049/mnl.2019.0252.
57. B. V. Chandan, K. Nigam, P. N. Kondekar, and D. Sharma, “Approach to suppress the ambipolar current conduction and improve radio-frequency performance in polarity control electrically doped hetero TFET,” IET Micro & Nano Letters, vol. 14, pp. 1033–1036, Sep. 2019, doi: https://doi.org/10.1049/mnl.2018.5598.
58. B. V. Chandan, K. Nigam, S. Tirkey, and D. Sharma, “Metal-strip approach on junctionless TFET in the presence of positive charge,” Applied Physics A, vol. 125, pp. 665–670, Aug. 2019, doi: https://doi.org/10.1007/s00339-019-2966-1.
59. B. V. Chandan, K. Nigam, and D. Sharma, “Approach on electrically doped TFET for suppression of ambipolar and improving RF performance,” IET Circuits, Devices & Systems, vol. 13, pp. 787–792, Jul. 2019, doi: https://doi.org/10.1049/iet-cds.2018.5394.
60. B. V. Chandan, K. Nigam, V. A. Tikkiwal, and D. Sharma, “Impact of hetero dielectric on the device electrical and linearity characteristics of electrically doped tunnel FET,” Advanced Science, Engineering and Medicine, vol. 11, pp. 484–490, 2019, doi: https://doi.org/10.1166/asem.2019.2386.
61. S. Kumar, K. S. Singh, K. Nigam, V. A. Tikkiwal, and B. V. Chandan, “Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance,” Applied Physics A, vol. 125, Art. no. 353, Apr. 2019, doi: https://doi.org/10.1007/s00339-019-2650-5.
62. B. V. Chandan, M. Gautami, K. Nigam, D. Sharma, V. A. Tikkiwal, S. Yadav, and S. Kumar, “Impact of a metal-strip on a polarity-based electrically doped TFET for improvement of DC and analog/RF performance,” Journal of Computational Electronics, vol. 17, pp. 76–82, Nov. 2018, doi: https://doi.org/10.1007/s10825-018-1280-z.
63. B. V. Chandan, K. Nigam, D. Sharma, and S. Pandey, “A novel methodology to suppress ambipolarity and improve the electronic characteristics of polarity-based electrically doped tunnel FET,” Applied Physics A, vol. 125, Art. no. 81, Jan. 2019, doi: https://doi.org/10.1007/s00339-019-2378-2.
64. B. V. Chandan, S. Dasari, K. Nigam, S. Yadav, S. Pandey, and D. Sharma, “Impact of gate material engineering on ED-TFET for improving DC/analogue-RF/linearity performances,” IET Micro & Nano Letters, vol. 13, pp. 1653–1656, Dec. 2018, doi: https://doi.org/10.1049/mnl.2018.5131.
65. S. Gupta, D. Sharma, S. Yadav, M. Aslam, D. S. Yadav, D. Soni, K. Nigam, and N. Sharma, “Examination of the impingement of interface trap charges on heterogeneous gate dielectric dual material control gate tunnel field effect transistor for the refinement of device reliability,” IET Micro & Nano Letters, vol. 13, pp. 1192–1196, Aug. 2018, doi: https://doi.org/10.1049/mnl.2017.0869.
66. B. V. Chandan, K. Nigam, D. Sharma, and S. Pandey, “Impact of interface trap charges on dopingless tunnel FET for enhancement of linearity characteristics,” Applied Physics A, vol. 124, Art. no. 503, Jun. 2018, doi: https://doi.org/10.1007/s00339-018-1923-8.
67. K. Nigam, S. Gupta, S. Pandey, D. Sharma, and P. N. Kondekar, “Controlling the ambipolarity and improvement of RF performance using Gaussian drain doped TFET,” International Journal of Electronics, vol. 105, pp. 806–816, Oct. 2017, doi: https://doi.org/10.1080/00207217.2017.1409807.
68. B. V. Chandan, K. Nigam, and D. Sharma, “Junctionless based dielectric modulated electrically doped tunnel FET based biosensor for label-free detection,” IET Micro & Nano Letters, vol. 13, pp. 452–456, Apr. 2018, doi: https://doi.org/10.1049/mnl.2017.0580.
69. B. Ram Raad, D. Sharma, P. N. Kondekar, K. Nigam, and S. Baronia, “DC and analog/RF performance optimisation of source pocket dual work function TFET,” International Journal of Electronics, vol. 104, pp. 1992–2006, May 2017, doi: https://doi.org/10.1080/00207217.2017.1335788.
70. B. Awadhiya, S. Pandey, K. Nigam, and P. N. Kondekar, “Effect of ITCs on linearity and distortion performance of junctionless tunnel field effect transistor,” Superlattices and Microstructures, vol. 111, pp. 293–301, Jun. 2017, doi: https://doi.org/10.1016/j.spmi.2017.06.036.
71. S. Gupta, K. Nigam, S. Pandey, D. Sharma, and P. N. Kondekar, “Effect of interface trap charges on performance variation of heterogeneous gate dielectric junctionless-TFET,” IEEE Transactions on Electron Devices, vol. 64, pp. 4731–4737, Sep. 2017, https://ieeexplore.ieee.org/document/8053895/.
72. P. Venkatesh, K. Nigam, S. Pandey, D. Sharma, and P. N. Kondekar, “A dielectrically modulated electrically doped tunnel FET for application of label free biosensor,” Superlattices and Microstructures, vol. 109, pp. 470–479, May 2017, doi: https://doi.org/10.1016/j.spmi.2017.05.035.
73. A. Gedam, S. Tirkey, K. Nigam, S. Pandey, D. Sharma, and P. N. Kondekar, “Investigation of gate material engineering in junctionless TFET to overcome the trade-off between ambipolarity and RF/linearity metrics,” Superlattices and Microstructures, vol. 109, pp. 307–315, Mar. 2017, doi: https://doi.org/10.1016/j.spmi.2017.03.059.
74. K. Nigam, S. Pandey, P. N. Kondekar, D. Sharma, and Pawan, “A barrier controlled charge plasma based TFET with gate engineering for ambipolar suppression and RF/linearity performance improvement,” IEEE Transactions on Electron Devices, vol. 64, pp. 2751–2757, Apr. 2017, https://ieeexplore.ieee.org/document/7907217.
75. K. Nigam, S. Pandey, P. N. Kondekar, D. Sharma, M. Verma, and A. Gedam, “Performance estimation of polarity controlled electrostatically doped tunnel field effect transistor,” IET Micro & Nano Letters, vol. 12, pp. 239–244, Apr. 2017, doi: https://doi.org/10.1049/mnl.2016.0729.
76. B. Ram Raad, D. Sharma, K. Nigam, and P. N. Kondekar, “Utility of III–V group ternary compound semiconductor materials for unipolar conduction in tunnel field-effect transistors,” Journal of Computational Electronics, vol. 16, pp. 24–29, Nov. 2016, doi: https://doi.org/10.1007/s10825-016-0932-0.
77. P. Venkatesh, K. Nigam, S. Pandey, D. Sharma, and P. N. Kondekar, “Impact of interface trap charges on reliability of heterogeneous gate dielectric electrically doped tunnel FET,” IEEE Transactions on Device and Materials Reliability, vol. 17, pp. 245–252, Jan. 2017, https://ieeexplore.ieee.org/document/7817872.
78. D. Sharma, B. R. Raad, D. Yadav, P. N. Kondekar, and K. Nigam, “Two-dimensional potential, electric field and drain current model of source pocket hetero gate dielectric triple work function tunnel field-effect transistor,” IET Micro & Nano Letters, vol. 12, pp. 11–16, Jan. 2017, doi: https://doi.org/10.1049/mnl.2016.0351.
79. M. Verma, D. Sharma, S. Pandey, K. Nigam, and P. N. Kondekar, “Performance comparison of single and dual metal dielectrically modulated TFETs for the application of label free biosensor,” Superlattices and Microstructures, vol. 101, pp. 219–227, Nov. 2016, doi: https://doi.org/10.1016/j.spmi.2016.11.045.
80. P. N. Kondekar, K. Nigam, S. Pandey, and D. Sharma, “Design and analysis of polarity controlled electrically doped tunnel FET with bandgap engineering for analog/RF applications,” IEEE Transactions on Electron Devices, vol. 64, pp. 412–418, Dec. 2016, https://ieeexplore.ieee.org/abstract/document/7801013
81. D. Singh, S. Pandey, K. Nigam, D. Sharma, D. S. Yadav, and P. N. Kondekar, “A charge-plasma-based dielectric-modulated junctionless TFET for biosensor label-free detection,” IEEE Transactions on Electron Devices, vol. 64, pp. 271–278, Nov. 2016, https://ieeexplore.ieee.org/document/7738525
82. K. Nigam, P. N. Kondekar, D. Sharma, and B. R. Raad, “A new approach for design and investigation of junction-less tunnel FET using electrically doped mechanism,” Superlattices and Microstructures, vol. 98, pp. 1–7, Jul. 2016, doi: https://doi.org/10.1016/j.spmi.2016.07.016.
83. K. Nigam, S. Pandey, P. N. Kondekar, and D. Sharma, “Temperature sensitivity analysis of polarity controlled electrostatically doped tunnel field-effect transistor,” Superlattices and Microstructures, vol. 97, pp. 598–605, Jul. 2016, doi: https://doi.org/10.1016/j.spmi.2016.07.023.
84. B. R. Raad, D. Sharma, P. N. Kondekar, K. Nigam, and D. S. Yadav, “Drain work function engineered doping-less charge plasma TFET for ambipolar suppression and RF performance improvement: A proposal, design, and investigation,” IEEE Transactions on Electron Devices, vol. 63, pp. 3950–3957, Aug. 2016, https://ieeexplore.ieee.org/document/7549035
85. K. Nigam, P. N. Kondekar, and D. Sharma, “Approach for ambipolar behavior suppression in tunnel FET by workfunction engineering,” IET Micro & Nano Letters, vol. 11, pp. 460–464, May 2016, doi: https://doi.org/10.1049/mnl.2016.0178.
86. B. R. Raad, D. Sharma, K. Nigam, and P. N. Kondekar, “Physics-based simulation study of high-performance gallium arsenide phosphide–indium gallium arsenide tunnel field-effect transistor,” IET Micro & Nano Letters, vol. 11, pp. 366–368, Jul. 2016, doi: https://doi.org/10.1049/mnl.2016.0050.
87. K. Nigam, P. N. Kondekar, and D. Sharma, “High frequency performance of dual metal gate vertical tunnel field effect transistor based on work function engineering,” IET Micro & Nano Letters, vol. 11, pp. 319–322, Jun. 2016, doi: https://doi.org/10.1049/mnl.2015.0526.
88. B. R. Raad, K. Nigam, D. Sharma, and P. N. Kondekar, “Performance investigation of band, gate material work function and gate dielectric engineered TFET with device reliability improvement,” Superlattices and Microstructures, vol. 94, pp. 138–146, Apr. 2016, doi: https://doi.org/10.1016/j.spmi.2016.04.016.
89. K. Nigam, P. N. Kondekar, D. Sharma, and B. R. Raad, “DC characteristics and analog/RF performance of novel polarity control GaAs–Ge based tunnel field effect transistor,” Superlattices and Microstructures, vol. 92, pp. 224–231, Jan. 2016, doi: https://doi.org/10.1016/j.spmi.2016.01.032. 
90. B. R. Raad, K. Nigam, D. Sharma, and P. N. Kondekar, “Dielectric and workfunction engineered TFET for ambipolar suppression and RF performance enhancement,” Electronics Letters, vol. 52, pp. 770–772, Apr. 2016, doi: https://doi.org/10.1049/el.2015.4348.

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Book Chapters:

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International & National Conference Proceedings:

1. P. Gupta, S. Singh Chauhan, K. Nigam, D. Kumar, J. Madan and R. Devlal, “Achieving 23.82% Efficiency in Lead-Free Cs2ScAgI6 Perovskite Solar Cells Using Fully Inorganic Charge Transport Layers,” 4th International Conference on Device Intelligence, Computing and Communication Technologies (DICCT), Dehradun, India, pp. 181-186, 2026, IEEE.
2. A. Tanveer, K. Nigam, B. V. Chandan, and J. Madan, “Enhancement in PSC parameters through Simulation of FAPbI₃ based HTL-free PSC using SCAPS-1D,” 6th International Conference on Advances in Steel, Power and Construction Technology, Taylor & Francis, Dec. 2025, in-press.
3. A. Tanveer, K. Nigam, B. V. Chandan, and E. A. Siddiqui, “Modelling and Simulation of Heterojunction TFETs: Tackling Performance Challenges Through Machine Learning and Advanced Computational Techniques,” 6th International Conference on Information Management & Machine Intelligence, pp. 1–7, Dec. 2024, ACM.
4. D. Kosre, B. V. Chandan, A. S. Raghuvanshi, and K. Nigam, “Analyzing Trap Charge Impact in Dopant Hetero-Material TFET via Interface Engineering,” 10th International Conference on Signal Processing and Communication (ICSC), pp. 750–754, Feb. 2025, IEEE.
5. M. K. Bind, P. Kwatra, V. A. Tikkiwal, S. V. Singh, and K. Nigam, “Simulation-Based Sensitivity Analysis of GaAs/GaSb Heterojunction Polarity-Controlled TFET for Biosensing Applications,” 10th International Conference on Signal Processing and Communication (ICSC), pp. 893–898, Feb. 2025, IEEE.
6. R. Kumar, B. V. Chandan, K. Nigam, A. Kumar, A. Tanveer, and H. Kumar, “Design and Simulation of High-Sensitivity AlGaN/GaN Based MOS-HEMT Biosensor for Biomolecule Detection,” 10th International Conference on Signal Processing and Communication (ICSC), pp. 791–796, Feb. 2025, IEEE.
7. M. P. Bakshi, B. V. Chandan, K. Nigam, A. Kumar, A. Tanveer, and A. Vaddeswarapu, “Enhancing Dopingless TFETs with SiGe Heterojunctions: A Reliability Perspective,” 10th International Conference on Signal Processing and Communication (ICSC), pp. 809–813, Feb. 2025, IEEE.
8. A. K. Singh, B. V. Chandan, K. Nigam, A. Kumar, A. Tanveer, and N. Dharmender, “Temperature-Dependent Sensing Properties of SOI-SDG-FinFET for Chemical Detection,” 10th International Conference on Signal Processing and Communication (ICSC), pp. 922–926, Feb. 2025, IEEE.
9. M. K. Bind, S. V. Singh, and K. Nigam, “Sensitivity Analysis of a Polarity-Controlled Tunnel Field-Effect Transistor-Based Biosensor,” 10th International Conference on Signal Processing and Communication (ICSC), pp. 882–887, Feb. 2025, IEEE.
10. A. Tanveer, K. Nigam, and B. V. Chandan, “A Promising Design to Enhance the Performance of HTL-Free and Pb-Free PSC,” Fourth International Conference on Power, Control and Computing Technologies (ICPC2T), pp. 1–5, Jan. 2025, IEEE.
11. B. V. Chandan, Dharmender, K. Nigam, and P. S. Subbarao, “Impact of Dual Oxide on Charge Plasma-Based Junctionless Tunnel Field Effect Transistor,” International Conference on Circuits and Communication Systems (ICICACS), Raichur, India, pp. 1–5, Feb. 2024, IEEE.
12. B V. Chandan, Dharmender, and  K. Nigam, “A Novel Approach to Enhance the Performance of TFET Using Metal Strip Layer for High-Frequency Applications,” International Conference on Modeling, Simulation & Intelligent Computing (MoSICom), Dubai, UAE, pp. 339–344, Dec. 2023, IEEE.
13. P. Kwatra, S. V. Singh, and K. Nigam, “Electrical Noise Analysis of Polarity Gate JLTFET,” 9th International Conference on Signal Processing and Communication (ICSC), Noida, India, pp. 638–643, Dec. 2023, IEEE.
14. M. K. Bind, S. V. Singh, and K. Nigam, “Design and Performance Assessment of a Si/GaSb-PC-TFET for Label-Free Bio-Sensing Applications,” 9th International Conference on Signal Processing and Communication (ICSC), Noida, India, pp. 663–668, Dec. 2023, IEEE.
15. S. Maturkar, Dharmender, and K. Nigam, “Metal Strip Layer Approach to Enhance the DC Characteristics and Analog/RF Performance of a Dual Material Control Gate TFET,” 9th International Conference on Signal Processing and Communication (ICSC), Noida, India, pp. 732–737, Dec. 2023, IEEE.
16. B. V. Chandan, Dharmender, P. S. Subbarao, and K. Nigam, “Examination of Interface Trap Charges on Electrically Doped Tunnel FET in the Presence of High-K Dielectric,” 7th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), Kolkata, India, pp. 1–6, Dec. 2023, IEEE.
17. Sangeedh, A. S. Raghuvanshi, Dharmender, M. Shreyanshi, and K. K. Nigam, “Investigation of DC Performance of TFET Using Dielectric Pocket at Source and Drain Side,” First International Conference on Advances in Electrical, Electronics and Computational Intelligence (ICAEECI), pp. 1–8, Dec. 2023, IEEE.
18. P. Kwatra, K. Nigam, and S. V. Singh, “Performance Analysis and Design of Hetero-Dielectric Heterojunction JLTFET with Impact of Interface Traps for Analogue and RF Applications,” 8th International Conference on Signal Processing and Communication (ICSC), pp. 638–643, Dec. 2022, IEEE.
19. M. K. Bind, K. Nigam, and S. V. Singh, “Polarity Control SiGe Source Tunnel Field Effect Transistor-Based Biosensor for Bio-Sensing Applications,” 8th International Conference on Signal Processing and Communication (ICSC), pp. 648–652, Dec. 2022, IEEE.
20. S. Kumar, K. S. Singh, and K. Nigam, “Negative Capacitance FET for Ultra Low Power Applications: A Review,” 8th International Conference on Signal Processing and Communication (ICSC), pp. 630–633, Dec. 2022, IEEE.
21. K. S. Singh, S. Kumar, and K. Nigam, “Vertical Tunneling Based Dual Material Double Gate TFET,” International Conference on Computing, Communication, and Intelligent Systems (ICCCIS), pp. 900–904, Feb. 2021, IEEE.
22. K. S. Singh, S. Kumar, and K. Nigam, “Tunnel Field Effect Transistor Based Biosensors: A Review,” 7th International Conference on Signal Processing and Communication (ICSC), pp. 391–395, Nov. 2021, IEEE.
23. Dharmender, K. Nigam, and S. Kumar, “III-V/Si Heterojunction Based Dual Material Stack Gate Oxide TFETs for Low Power Applications,” 7th International Conference on Signal Processing and Communication (ICSC), pp. 330–336, Nov. 2021, IEEE.
24. P. Kwatra, K. Nigam, and S. V. Singh, “Performance Analysis of Novel Heterojunction ESDG-TFET for Analogue/RF Applications,” 7th International Conference on Signal Processing and Communication (ICSC), Nov. 2021, IEEE.
25. P. Verma, S. Kumar, and K. Nigam, “Performance Analysis of Stack Gate Oxide Underlap TFET Utilising Metal Strip Mechanism,” 7th International Conference on Signal Processing and Communication (ICSC), pp. 372–376, Nov. 2021, IEEE.
26. Nishad, K. Nigam, V. A. Tikkiwal, and S. Kumar, “Performance Analysis of Double Gated GaAs-Ge Based Hetero Tunnel Field Effect Transistor,” 6th International Conference on Signal Processing and Communication (ICSC), pp. 284–287, Mar. 2020, IEEE.
27. K. S. Singh, S. Kumar, K. Nigam, and V. A. Tikkiwal, “Tunnel Field Effect Transistor for Ultra Low Power Applications: A Review,” International Conference on Signal Processing and Communication (ICSC), pp. 286–291, Mar. 2019, IEEE.
28. S. Gupta, K. Nigam, S. Pandey, D. Sharma, and P. N. Kondekar, “Performance Improvement of Heterojunction Double Gate Drain Overlapped TFET Using Gaussian Doping,” Energy Efficient Electronic Systems and Steep Transistors Workshop (E3S), Fifth Berkeley Symposium, Berkeley, CA, USA, Oct. 2017, IEEE.
29. B. V. Chandan, K. Nigam, S. Pandey, D. Sharma, and P. N. Kondekar, “Temperature Sensitivity Analysis on Analog/RF and Linearity Metrics of Electrically Doped Tunnel FET,” Conference on Information and Communication Technology (CICT), pp. 1–5, Nov. 2017, IEEE.
30. K. Nigam, S. Pandey, P. N. Kondekar, and D. Sharma, “Temperature Sensitivity Analysis of Polarity Controlled Electrically Doped Hetero-TFET,” 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 1–4, Jun. 2016, IEEE.
31. S. Baronia, K. Nigam, D. S. Yadav, D. Sharma, B. R. Raad, and P. Kondekar, “A Novel Approach of PNPN Dual Metal Double Gate Tunnel Field Effect Transistor for Improving DC Characteristics,” International Conference on Advanced Communication Control and Computing Technologies, pp. 44–47, May 2016, IEEE.
32. S. Pandey, P. N. Kondekar, K. Nigam, and D. Sharma, “A 0.9 V, 3.1–10.6 GHz CMOS LNA with High Gain and Wideband Input Match in 90 nm CMOS Process,” Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 730–733, Oct. 2016, IEEE.

Patents Published:

Educational Qualifications:

• Doctor of Philosophy (Ph.D.), Department of Electronics & Communication Engineering, Indian Institute of Information Technology (IIIT), Jabalpur, Madhya Pradesh, India. Awarded: April 2018
• Master of Technology (M.Tech.), Department of Electronics & Communication Engineering, National Institute of Technology (NIT), Bhopal, Madhya Pradesh, India. Awarded: June 2011
• Bachelor of Technology (B.Tech.), Department of Electronics & Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India. Awarded: June 2009

Work Experience:

• Currently working as an Associate Professor at the Department of Electronics and Communication Engineering, National Institute of Technology Raipur, C.G., India.
• Worked as an Assistant Professor at the Department of Electronics and Communication Engineering, National Institute of Technology Raipur, C.G., India
• Worked as an Assistant Professor (Sr. Grade) at the Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida, U.P., India.

Research Supervision:

    Ph.D. Supervised:

• Mukesh Kumar Bind, “Design and Performance Analysis of a Polarity-Controlled Dielectric-Modulated TFET”,  March 2026. (Role: Joint Supervisor).
• Priyanka Kwatra, “Design and Reliability Improvement of Tunnel Field Effect Transistor”, September 2023. (Role: Joint Supervisor).
• Dharmender, “Design and Performance Analysis of Tunnel Field Effect Transistor and Its Applications”, June 2023. (Role: Supervisor).
• K M. Sucheta Singh, “Design and Performance Investigation of Tunnel Field Effect Transistor and Its Applications”, January 2022. (Role: Joint Supervisor).

   Ph.D. in Progress:

• Adil Tanveer, “Multiple Absorber all Inorganic and Hybrid Perovskite Solar Cell”, (Role: Supervisor).
• Bandi Venkata Chandan, “Design, Performance Analysis and Reliability Improvement of Tunnel Field Effect Transistor”, (Role: Supervisor).
• Parvin Akhter, “Multiple Absorber all Inorganic and Hybrid Tandom Solar Cell”, (Role: Supervisor).
• Kunal Gupta, “Modeling and Performance Analysis of Advanced Semiconductor Devices for Next-Generation Electronics”, (Role: Joint Supervisor).
• Vaddeswarapu Ashok, “Design and Reliability Assessment of Tunnel Field-Effect Transistors”, (Role: Joint Supervisor).
• Hitesh Kumar, “Design and Performance Analysis of Metal Oxide Semiconductor-High Electron Mobility Transistor (MOS-HEMT) for Biosensing Applications”, (Role: Joint Supervisor)
• Ashish Patle, “Design and Performance Analysis of Vertical Tunnel Field-Effect Transistor for Biosensing Applications”, (Role: Joint Supervisor).

   M.Tech. Supervised:

• Gadi Harshavardhan (Roll No. 24266001), “Design and Performance Evalution of Dual-Material Gate Charge Plasma TFET using TCAD Simulation and Machine Learning”, June 2026. (Role: Supervisor)
• Thathireddy Hari Sree (Roll No. 24266020), “Performance Analysis of Chalcogenide Perovskite Solar Cells for Efficiency Improvement Using SCAPS-1D Simulation and Machine Learning”, June 2026. (Role: Supervisor)
• Rakesh Kumar (Roll No. 23266013), “Design and Performance Evaluation of Dielectric-Modulated MOS-HEMT Biosensors for Biomolecular Detection”, June 2025. (Role: Supervisor)
• Ajay Kumar Singh (Roll No. 23266001), “Design and Simulation of Stack Gate based FinFET for Hydrogen Gas and Chemical Sensing Applications”, June 2025.  (Role: Supervisor)
• Madhura Prashant Bakshi (Roll No. 23266007), “Design and Performance Study of Charge Plasma Tunnel FETs Considering Trap Charges and Temperature Effects”, June 2025. (Role: Supervisor)
• Sangeedh (Roll No. 22266008), “Dual Material Stack Gate Oxide Tunnel FET with Dielectric Pockets: Performance Analysis and Applications”, June 2024. (Role: Supervisor)
• Shreyanshi Maturkar (Roll No. 22266011), “Performance Analysis and Investigation of Dual Material Control Gate TFETs Based on Metal Strip for Enhanced Analog/RF and Mole Fraction Engineering for Biosensing Applications”, June 2024. (Role: Supervisor)

   B.Tech Minor/Major Project Supervised:

• Gottumukkala Bhanu Jahnavi (Roll No. 22116037), and Sumala Mourya Karnika (Roll No. 22116101), “Design and Analysis of Electrically Doped Mg₂Si-based TFET for Gas Sensing Applications”, May 2026.
• Polavarapu Keertana (Roll No. 22116075), “Design and Analysis of Vertical Heterojunction TFETs for Low-Power Gas Detection Application”, May 2026.
• Priyal Soni (Roll No. 22116083), and Saketi Sai Venkata Raja Rao (Roll No. 22116090), “Design and Performance Evaluation of Heterojunction based Z-Shaped TFET under Thermal Reliability”, May 2026.
• Dangeti Balu Satish Kumar (Roll No. 22116028) and Mohammad Arish Khan (Roll No. 22116061), “Integration of Machine Learning Approach on CsSn_0.5Ge_0.5I₃ Perovskite Solar Cells”, May 2026.
• Gottumukkala Bhanu Jahnavi (Roll No. 22116037), and Sumala Mourya Karnika (Roll No. 22116101), “Impact of Reliability Factors on the Performance of Electrically Doped Tunnel FET”, December 2025.
• Mohammad Arish Khan (Roll No. 22116061), and Polavarapu Keertana (Roll No. 22116075), “Machine Learning Based Modelling of Double-Gated Tunnel FET Characteristics”, December 2025.
• Priyal Soni (Roll No. 22116083), and Saketi Sai Venkata Raja Rao (Roll No. 22116090), “Design and Simulation of Graphene-Based Electrically Doped MOSFET for Hydrogen Sensing”, December 2025.
• Dangeti Balu Satish Kumar (Roll No. 22116028), “Comparative Analysis of Electron Transport Layer for High Efficiency Perovskite Solar Cells Using SCAPS”, December 2025.
• Anand Kumar Patel (Roll No. 21116007), “Sensitivity Analysis of Hydrogen Gas on Electrically Doped MOSFET”, May 2025.
• Mansi (Roll No. 21116065), “Modeling and Analysis of Electrically Doped MOSFET for Polymer Gas Detection Applications”, May 2025.
• Anand Kumar Patel (Roll No. 21116007), “Effect of Interface Trap Charges on Dual Material Gate Junctionless Tunnel Field Effect Transistor”, December 2024.
• Anurag Deo (Roll No. 21116014), “Temperature Analysis of Z-Shaped Tunnel Field Effect Transistor”, December 2024.
• Ishaan Adarsh (Roll No. 21116044), “Interface Trap Analysis in Z-Shaped Tunnel Field Effect Transistor”, December 2024.
• Mansi (Roll No. 21116065), “Trap Analysis of Mg₂Si/Si Junction Based Electrically Doped Tunnel Field Effect Transistor (TFET)”, December 2024.
• Pratyush Nagpal (Roll No. 21116082), “Enhancement of Z-Shape Mg₂Si/Si Interface Junction in TFET”, December 2024. 
• Raju Kumar (Roll No. 21116090), “Design and Optimization of Dopant-Free Vertical TFET in the Presence of Temperature”, December 2024. 
• Abhinav Srinivas Ivaturi (Roll No. 21116003), “Impact of Dual Metal Gate on Tunnel Field Effect Transistor”, December 2024.
• Kuldeep Sahu and Vivek Sharma, “Design and Performance Analysis of InGaN Solar Cell in Silvaco ATLAS”, May 2024.
• Khageshwar Singh, “Junctionless Tunnel Field Effect Transistor Based Biosensor”, May 2024.
• Ram Pravesh Kumar, “DG-TFET Biosensor Simulation and Analysis for Various Biomolecules”, May 2024.
• G. S. V. D. Surya Prakash, “DG-TFET Biosensor Simulation and Analysis for Various Biomolecules”, May 2024.
• Utkarsh Maurya, “TFET Based Biosensor”, May 2024.

Courses Taught (B.Tech./M.Tech./Ph.D.)

   Theory:

• EC41251VL: Low Power VLSI Design (Spring-2023, Spring-2024, Spring-2025)
• ET41333VL: Nano-Electronics (Autumn-2024)
• EC311201EC: Nano-Electronics (Autumn-2024)
• EC311101EC: Nanoscale Semiconductor Devices (Autumn-2025)
• EC106208EC: Semiconductor Device Modeling (Spring-2026)

   Laboratory:

• EC104404EC: Linear Integrated Circuits & Applications Laboratory (Spring-2023)
• EC41121VL: VLSI Design Laboratory-I (Autumn-2024)
• EC103401EC: Device and Circuit Laboratory (Autumn-2025)
• EC106402EC: VLSI Design Laboratory (Spring-2024, Spring-2026)

Training Programs/Seminars/Workshops Organized

• Electronics & ICT Sponsored Ten Days Faculty Development Program (FDP) on “Innovative Materials for Future Semiconductors Devices: Trends, Challenges, and Applications”, National Institute of Technology Raipur, 21^th-30^th April 2025. (Role: Coordinator)
• Five-day Self Sponsor Short-Term Training Program (STTP) on “Next Generation Wireless Technology: 5G and Its Impact on Smart Systems”, Guru Ghasidas Vishwavidyalaya, Bilaspur, C.G., 07^th-12^th April 2025. (Role: Coordinator)

Invited Expert Lectures/Talks/Seminars Delivered 

• Delivered expert lecture in E & ICT FDP on "Innovative Materials for Future Semiconductors Devices: Trends, Challenges, and Applications”, organized by NIT Raipur and Guru Ghasidas Vishwavidyalaya, Bilaspur, India, 27^th April 2025.
• Delivered expert lecture in E & ICT FDP on "Semiconductor Devices and Circuits: Research Trends and Applications”, organized by NIT Warangal, T.S., India, 11^th November 2024.
• Delivered expert lecture in E & ICT FDP on "Research Trends and Applications of Nanoscale Devices and Circuits”, organized by NIT Warangal, T.S., India, 27^th September 2024.

Keynote Talks/Presentations in International Conferences 

• Presented on “A Novel Approach to Enhance the Performance of TFET using Metal Strip Layer for High-Frequency”, IEEE International Conference on Modelling, Simulation, and Intelligent Computing (MoSICom-2023), 07-09 December 2023, organized by BITS Pilani, Dubai Campus, UAE.

Contributions in Institute/Department Administration

   Academic Activities:

• Serving as Department Purchase Coordinator.
• Faculty-in-charge, Basic VLSI Laboratory.
• Served as Departmental In-charge of Accreditation.
• Served as Departmental Time Table In-charge.
• Member of the DST-funded FIST Project Implementation Group.
• Appointed as Departmental Faculty Advisor for 5^th Semester students.
• Faculty In-charge of Internships for 5^th and 7^th Semester students.
• Member of the End-Semester Examination Committee (result collation and declaration).
• Preparation of presentation reports for the Departmental Audit.
• Compilation and documentation for the Best Department Award.
• Question paper setter and examination duties for Ph.D. admissions.
• Mentoring students for technical competitions, projects, and career development.
• Supervising Ph.D. scholars and guiding research projects in semiconductor devices-based biosensors and Solar Cell.

   Administrative Responsibilities:

• Member of the NIRF Task Force Committee for institutional growth and ranking enhancement.
• Nodal Officer for Capacity Building on Specific Learning Disabilities for employees and students.

Other Professional/Extensional Services

Reviewer in Journals (Past five years)

• IEEE Transactions on Electron Devices (TED)
• IEEE Electron Device Letters (EDL)
• IEEE Transactions on Device and Materials Reliability (TDMR)
• IEEE Transactions on Nanotechnology (TNANO)
• IEEE Journal on Flexible Electronics
• IEEE transactions on Consumer Electronics
• IEEE Sensor Journal
• Micro and Nanostructure (Elsevier)
• Solid-State Electronics (Elsevier)
• Microelectronics Journal (Elsevier)
• Integration, the VLSI Journal (Elsevier)
• AEÜ – International Journal of Electronics and Communications (Elsevier)
• Silicon (Springer)
• Journal of Computational Electronics (Springer)
• Journal of Electronic Materials (Springer)
• Applied Physics A (Springer)
• Journal of Materials Science: Materials in Electronics (Springer)
• Microsystem Technologies (Springer)
• Analog Integrated Circuits and Signal Processing (Springer)
• Semiconductor Science and Technology (IOP)
• Physica scripta (IOP)

Student Support Resources

   Courses Link:

• NPTEL Courses on Semiconductor Devices for Next Generation Field Effect Transistors
• NPTEL Courses on Semiconductor device modeling and Simulation
• NPTEL Courses on Basic Overview of Semiconductor Device Processing and IC Fabrication
• NPTEL Courses on Low Power VLSI Circuits & Systems
• NPTEL Courses on Nanoelectronics: Devices and Materials
• NPTEL Courses on Physics of Nanoscale Devices

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