::: National Institute of Technology Raipur :::

Dr. Alok Naugarhiya

Department	Electronics & Telecom. Engineering
Designation	Assistant Professor
Educational Qualification	BE (EC), M.Tech (Microelectronics and VLSI Design), Ph.D. (ECE)
E-Mail	anaugarhiya.etc@nitrr.ac.in
Contact Number	8989828339

Areas of Interest

VLSI design, semiconductor device modeling, analysis of superjunction power MOSFET, high-k devices, silicon carbide use in high power devices and strain effect on semiconductor power devices.

Publications

Google Scholar link

https://scholar.google.co.in/citations?hl=en&user=bsEsv5wAAAAJ

International Journal Publications

Year 2024

A Ray, A Naugarhiya, GP Mishra “Improved post-radiation behavior of FinFET based CMOS with workfunction modulated gate”, Physica Scripta, Volume 99, Number 4, March 2024. DOI 10.1088/1402-4896/ad3386

Abhishek Ray, Alok Naugarhiya, Guru Prasad Mishra, “TID response of hybrid FinFET with modified gate dielectric”, Micro and Nanostructures, Volume 187, January 2024. DoI: https://doi.org/10.1016/j.micrna.2024.207759.

Year 2023

A Ray, A Naugarhiya, GP Mishra “Total ionizing dose effect of bulk and SOI P-FinFET with linear workfunction modulation technology” Microelectronics Journal Vol.137, pp. 105822(2023).

R Singh, A Naugarhiya, GP Mishra “Endurance behaviour of Z-shaped charge plasma Tunnel FET for biosensing application” Journal of Circuits, Systems and Computers (2023).

Year 2022

M Vaidya, A Naugarhiya, S Verma, GP Mishra “1.2 kV Stepped Oxide Trench Insulated Gate Bipolar Transistor with Low Loss for Fast Switching Application” ECS Journal of Solid State Science and Technology. Vol. 11, pp. 111008 (2022).

A Ray, A Naugarhiya, GP Mishra “ Analysis of total ionizing dose response of optimized fin geometry workfunction modulated SOI-FinFET ” journal of Microelectronics Reliability , Vol. 134, pp. 114549 (2022).

N Gupta, P Roy, A Naugarhiya “Design and investigation of split (n/n-) buffer layer semi-superjunction IGBT” Journal of Applied Physics A , Vol. 128 , pp. 376 (2022).

N Gupta, P Roy, O Parmar, A Naugarhiya “Plasma Enhancement Semi-Superjunction Trench IGBT with Higher Figure-of-Merit” Journal of Electronic Materials , Vol. 51 , pp. 2576-2585 (2022).

O Parmar, N Gupta, A Naugarhiya “Reduction in area‐specific on‐resistance with vertical stepped doped high‐k VDMOS” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields , Vol. 35 , pp. e2979 (2022).

V Butram, A Naugarhiya “Performance enhancement of piezoelectric mems energy harvester using split proof mass for powering ultralow power wireless sensor nodes” Arabian Journal for Science and Engineering , Vol. 47 , pp. 2755-2762 (2022).

M Vaidya, A Naugarhiya, S Verma, GP Mishra “Collector engineered bidirectional insulated gate bipolar transistor with low loss” Journal of IEEE Transactions on Electron Devices, Vol. 69 , pp. 1604-1607 (2022).

Year 2021

V Butram, A Mishra, A Naugarhiya “A lead-free spiral bimorph piezoelectric mems energy harvester for enhanced power density” IETE Technical Review , Vol. 38 , pp. 537-546 (2021).

O Parmar, A Naugarhiya “High temperature analysis of strained superjunction vertical single diffused MOSFET” International Journal of Modern Physics B , Vol. 35 , pp. 2150196 (2021).

M Vaidya, A Naugarhiya, S Verma, GP Mishra “A low-loss variable-doped trench-insulated gate bipolar transistor with reduced on-state voltage” Semiconductor Science and Technology , Vol. 36, pp. 075002 (2021).

S Agarwal, S Singh, BC Sahana, A Naugarhiya “Gaussian doped planar 4H-SiC junctionless field effect transistor for enhanced gate controllability” silicon , Vol. 13 , pp. 1609-1618 (2021).

N Gupta, A Naugarhiya “The design of a new heterogate superjunction insulated-gate bipolar transistor” Journal of Computational Electronics , Vol. 20 , pp. 883-891 (2021).

N Gupta, A Naugarhiya “1.4kV Planar Gate Superjunction IGBT with Stepped Doping Profile in Drift and Collector Region” Silicon, Vol.13, pp. 697-706 (2021). https://doi.org/10.1007/s12633-020-00456-8

Raj, A., Singh, S., Priyadarshani, K.N. et al. “Vertically Extended Drain Double Gate Si1−xGex Source Tunnel FET : Proposal & Investigation For Optimized Device Performance” Silicon 13, 2589–2604 (2021). https://doi.org/10.1007/s12633-020-00603-1

KN Priyadarshani, S Singh, A Naugarhiya “Dual metal double gate Ge-Pocket TFET (DMG-DG-Ge-Pocket TFET) with hetero dielectric: DC & analog performance projections” silicon , pp. 1-12 (2021).

KN Priyadarshani, S Singh, A Naugarhiya “RF & linearity distortion sensitivity analysis of DMG-DG-Ge pocket TFET with hetero dielectric” Microelectronics Journal , Vol. 108 , pp. 104973 (2021).

H Kumar, S Singh, KN Priyadarshani, J Ghosh “Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields , vol. 34 ,pp. e2812 (2021).

Year 2020

S Singh, S Singh, A Naugarhiya “Optimization of si-doped hfO2 ferroelectric material-based negative capacitance junctionless tfet: impact of temperature on rf/linearity performance” International Journal of Modern Physics B , Vol. 34 , pp. 2050242 (2020).

N. Gupta, S. Singh, & A. Naugarhiya, “An insulated gate bipolar transistor with three-layer poly gate for improved figure of merit” Journal of Materials Science: Materials in Electronics Vol. 31, 15513–15521 (2020).

Vicky Butram, Ashutosh Mishra & Alok Naugarhiya, “A Lead-Free Spiral Bimorph Piezoelectric MEMS Energy Harvester for Enhanced Power Density, IETE Technical Review, 2020. DOI: 10.1080/02564602.2020.1799876

M. Vaidya, A. Naugarhiya, S. Verma and G. P. Mishra, "Lateral Variation-Doped Insulated Gate Bipolar Transistor for Low On-State Voltage With Low Loss," in IEEE Electron Device Letters, vol. 41, no. 6, pp. 888-891, June 2020. Doi: 10.1109/LED.2020.2986941.

M Vaidya, A Naugarhiya, S Verma” Trench IGBT with stepped doped collector for low energy loss”, Semicond. Sci. Technol. 35, 2020. DOI 10.1088/1361-6641/ab6106

O Parmar, P Baghel, A Naugarhiya “Novel strained superjunction vertical single diffused MOSFET”, AEU - International Journal of Electronics and Communications, Volume 113, 2020. DOI: https://doi.org/10.1016/j.aeue.2019.152929.

Year 2019

P Nautiyal, A Naugarhiya, S Verma “An Assessment of Step Patterned Gate Oxide Superjunction Trench MOSFET for Potential Benefits”, J. Electron. Mater. 48, 8156–8162 (2019). https://doi.org/10.1007/s11664-019-07657-x.

P.Nautiyal, A. Naugarhiya, S.Verma, “Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications”, Semicond. Sci. Technol. 34 095016, 2019. DOI 10.1088/1361-6641/ab337f.

P.Nautiyal, A. Naugarhiya, S.Verma, “Strained superjunction U-MOSFET with insulating layer between alternate pillars”, Mater. Res. Express 6 046424, 2019. DOI 10.1088/2053-1591/aaff1d.

Year 2018

O.Parmar, A. Naugarhiya, “Incorporation of hafnium and platinum metal in vertical power MOSFETs”, J Comput Electron 17, 1241–1248 (2018). https://doi.org/10.1007/s10825-018-1193-x.

Year 2017

P.Nautiyal, A. Naugarhiya, S.Verma, “Novel Application of workfunction engineering in vertical superjunction devices” Superlattices and Microstructures, Volume 109, Pages 927-935, 2017. DOI: https://doi.org/10.1016/j.spmi.2017.06.024.

A. Naugarhiya” A Novel Charge-Protection SuperjunctionInsulator VDMOS”, International Journal of Electronics and Electrical Engineering Vol. 5, No. 3, June 2017.

A Naugarhiya, P Wakhradkar, PN Kondekar, GC Patil, RM Patrikar, “Analytical model for 4H-SiC superjunction drift layer with anisotropic properties for ultrahigh-voltage applications” Journal of Computational Electronics, vol.16, no.1, pp.190-201, 2017.

Year 2015

A Naugarhiya, PN Kondekar, “High permittivity material selection for design of optimum Hk VDMOS” Superlattices and Microstructures, vol. 83, pp.310-321, 2015.

A Naugarhiya, PN Kondekar, “Novel strained superjunction VDMOS” Superlattices and Microstructures, vol. 83, pp.310-321, 2015.

International Conference Publications

Year 2024

S. P. Behera, M. Vaidya and A. Naugarhiya, "Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application," 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), Kolkata, India, 2024, pp. 1-5, doi: 10.1109/VLSID60093.2024.00005.

Year 2023

A. Naugarhiya, C. Das and M. Vaidya, "Insulated Gate Bipolar Transistors with Deep Trench Technology for Low Loss Switching Application," 2023 International Conference on Modeling, Simulation & Intelligent Computing (MoSICom), Dubai, United Arab Emirates, 2023, pp. 317-321, doi: 10.1109/MoSICom59118.2023.10458719.

S. Gupta, D. K. Meda and A. Naugarhiya, "SEGR Analysis of SJ_IGBT with High-k Gate Dielectrics for Radiation Environment," 2023 World Conference on Communication & Computing (WCONF), RAIPUR, India, 2023, pp. 1-5, doi: 10.1109/WCONF58270.2023.10235100.

MH Manzoor, A Ray, A Naugarhiya “ Analysis of GaAs FinFET Based Biosensor with Under Gate Cavity” 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS) , pp. 1-6 (2023).

S Singh, S Ranjan, A Naugarhiya “SEGR and SEB Analysis of SJVDMOS using SiO 2/Si 3 N 4 as Gate Dielectric with Buffer layer” 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS) ,pp. 1-6 (2023).

Year 2022

A Ray, A Naugarhiya, GP Mishra “ Influence of total ionizing dose on LWM Bulk and SOI p-FinFET ” IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON). pp. 421-425 (2022).

V Butram, A Naugarhiya “Analysis of Split Proof Mass Pieozoelectric Cantilever based MEMS Energy Harvesting System using Ultra Low Power Rectifier Circuit” IEEE Region 10 Symposium (TENSYMP) , pp. 1-4 (2022).

S Yogi, A Naugarhiya “Performance Optimization of IGZO-Based Junctionless Thin Film Transistor for Low Power Application” Proceedings of Fifth International Conference on Inventive Material Science Applications: ICIMA , pp. 285-294 (2022).

J Pavuluri, SM Ranjan, A Naugarhiya “Analysis of Gate Oxides in LDMOS for Radiation Hardening Against SEGR” International Conference on Intelligent Controller and Computing for Smart Power (ICICCSP) , pp. 1-6 (2022).

M Vaidya, A Naugarhiya, S Verma, GP Mishra “Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application” International Symposium on VLSI Design and Test , pp. 53-64 (2022).

M Amjath, S Ranjan, A Naugarhiya “SEGR Analysis of Super Junction VDMOS using HfO 2 as Gate Dielectric” Second International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT) , pp. 1-5 (2022).

N Gupta, A Naugarhiya “Capacitive Analysis of Superjunction Vertical IGBT with Gate Engineering” First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT) , pp. 1-5 (2022).

V Butram, A Ray, A Naugarhiya, GPSC Mishra “A Novel Concept of Roof Top Tip Mass in Cantilever Based Energy Harvester for Wireless Sensor Node” Proceedings of the 2nd International Conference on Data Science, Machine Learning and Applications , pp. 1497-1504 (2022).

Year 2021

A Ray, A Naugarhiya, GP Mishra “Study of Gate Workfunction Modulated FinFET with Effect of TID” Modern Electronics Devices and Communication Systems: Select Proceedings of MEDCOM , pp. 253-259(2021).

P. Nautiyal, A. Naugarhiya and S. Verma, “Performance evaluation of superjunction UMOS with dual polysilicon gate." Materials Today: Proceedings 46 (2021): 4546-4552.

M. Vaidya, A. Naugarhiya and S. Verma, “Lateral variation doped wide bottom trench gate IGBT for reduced on-resistance with improved gate charge." Materials Today: Proceedings 46 (2021): 4587-4592.

N. Gupta and A. Naugarhiya. “1.4 kv superjunction igbt with variation doping profile for enhanced performance parameters." Materials Today: Proceedings 46 (2021): 4800-4806.

A Ray, A Naugarhiya, GP Mishra “Influence of SET effects in low-doped double gate MOSFETs” Materials Today: Proceedings , Vol. 43 , pp. 3867-3873 (2021).

R Verma, S Ranjan, A Naugarhiya “Analysis of Single Event Gate Rupture in Trench Gate SJ-VDMOS with SiO 2-Si 3 N 4 Dielectric Stacking” IEEE Region 10 Symposium (TENSYMP) , pp. 1-6 (2021).

O Parmar, P Nautiyal, A Naugarhiya “Capacitive Analysis of Strained Superjunction Vertical Single Diffused MOSFET” Devices for Integrated Circuit (DevIC) , pp. 139-142 (2021).

KN Priyadarshani, S Singh, A Naugarhiya “Impact of Temperature on DC and Analog/RF Performance for DM-DG-Ge Pocket TFET” Proceedings of International Conference on Communication and Artificial Intelligence: ICCAI 2020 , pp.135-141 (2021).

Year 2020

A Chunn, A Agrawal, A Naugarhiya, “An 8T TG-DTMOS Based Subthreshold SRAM Cell with Improved Write Ability and Access Times”, 2020 24th International Symposium on VLSI Design and Test (VDAT), 1-6.

S. Ranjan, S. Majumder and A. Naugarhiya, "SEGR Hardened Superjunction VDMOS with High-K Gate Dielectrics," 2020 International Conference on Power Electronics & IoT Applications in Renewable Energy and its Control (PARC), Mathura, Uttar Pradesh, India, 2020, pp. 272-275, doi: 10.1109/PARC49193.2020.236606.

Year 2019

P.Nautiyal, A. Agrawal, S. Kumari, H. Sahu, A. Naugarhiya and S. Verma, “"Electrical characteristic investigation of variation vertical doping superjunction UMOS." In 2019 IEEE 16th India Council International Conference (INDICON), pp. 1-4. IEEE, 2019.

M. Vaidya, A. Naugarhiya, S. Verma, “"Design and Analysis of Improved IGBT with Embedded p+ in N-Buffer Layer." In 2019 IEEE 16th India Council International Conference (INDICON), pp. 1-4. IEEE, 2019.

P.Shukla, A. Chunn, A.Naugarhiya, “A robust 13T single ended Schmitt trigger based SRAM cell." In 2019 5th International Conference on Signal Processing, Computing and Control (ISPCC), pp. 329-334. IEEE, 2019.

V.Butram, A.Naugarhiya, “An Efficient Design of Spiral Shaped MEMS Energy Harvester for Low Power Electronic Applications." In 2019 5th International Conference on Signal Processing, Computing and Control (ISPCC), pp. 335-338. IEEE, 2019.

Ajeet Singh Lowanshi, Onika Parmar, Anshul Gupta and Alok Naugarhiya “An Effective Charge Plasma based Semi-Superjunction MOSFET”, 2nd IEEE - International Conference on Systems Computation Automation and Networking “29th and 30th March 2019, ICSCAN 2019, Puducherry, India.

S. Hafizullah, Mahesh Vaidya, Shrish Verma, Alok Naugarhiya, " An efficient hardware architecture for route discovery in AODV for a sensor node." In 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON), pp. 70-74. IEEE, 2019.

Prashant Kumar Kushwaha, Payal Nautiyal, Anshul Gupta, Alok Naugarhiya, Shrish Verma, “An improved SJ UMOS with modified gate electrode to reduce gate charge." In 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON), pp. 81-84. IEEE, 2019.

Abhishek Ray, Vicky Butram, Namrata Gupta, Alok Naugarhiya, " "Non-Conventional Cantilever for Piezoelectric Energy Harvesting at Ultra Low Resonant Frequency." In 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON), pp. 90-93. IEEE, 2019.

Year 2018

Shaik Hafizullah, M. S. S. V Srikrishna Manideep, Vinay Sharma, PallabKumar Nath, Alok Naugarhiya, Shrish Verma, “An Efficient Hardware Implementation of Walsh Hadamard Transform for JPEG XR”, 15th Edition of the IEEE India Council International Conference (INDICON), 2018, organised by Amrita Vishwa Vidyapeetham, Coimbatore.

Namrata Gupta, Abhishek Ray, Alok Naugarhiya, Abhinav Gupta "Design and Optimization of MEMS Piezoelectric Cantilever for Vibration Energy Harvesting Application", in VCAS-2018 organised by MNNIT Allahabad.

Vicky Batrum, Alok Naugarhiya, “Non traditional proof mass arrangement in cantilever based pizeoelectric energy harvester” in ICCCS 2018 organized at Katmandu Nepal.

Onika Parmar and Alok Naugarhiya, “Application of workfunction engineering in lateral power devices” in International Conference on Advacnces in Electronics Computers and Communication (ICAECC 2018) organized by, REVA University, Bangalore, India.

M Vaidya, A. Naugarhiya, S. Verma, “High Speed Generic Voltage Level Shifter” Second International Conference on Electronics, Computers and Communications (ICAECC-2018), REVA University, Bangalore, India.

P. Nautiyal, A. Naugarhiya, S. Verma, “Charge Plasma Based VVD-SJ VDMOS Employing Reversed Doping Concentration” Second International Conference on Electronics, Computers and Communications (ICAECC-2018), REVA University, Bangalore, India.

P. Nautiyal, O. Parmar A. Naugarhiya, S. Verma, “Design and Performance Projection of Workfunction Engineered Variable Vertical Doped Superjuction Vertical Single Diffused MOS” International Conference on Electronics, Computing and Communication Technologies (IEEE CONECCT 2018), Bangalore, India.

Ankush Chunn, A. Naugarhiya, “Use of Open Source CAD Tools in VLSI Design Curriculum for Developing Countries” International Conference on Computing, Engineering and Information Technology (ICCEIT 2018) ,Bangkok, Thailand.

Year 2017

A. Sharma, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma, “VERILOG based simulation of ASK, FSK, PSK, QPSK digital modulation techniques”, International conference on IoT in Social, Mobile, Analytics and Cloud (I-SMAC 2017).

A. Chakradhari, S. Tamrakar, R. Basant, M. Vaidya, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder and S. Verma “Slotted CSMA/CA Simulation in Verilog”, International Workshop on Internet of Things and TV White Spaces (WIOT’ 2017).

A. Chaudhary, J. Rusia, K. Gourav, P. Tripathi, J. Pandey, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma, “Design and Simulation of Physical Layer Blocks of ZigBee Transmitter”, International conference on IoT in Social, Mobile, Analytics and Cloud (I-SMAC 2017).

Year 2016

J. Rusia, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma “Remote Temperature & Humidity sensing through ASK Modulation Technique”, International Conference on ICT in Business Industry Government (ICTBIG 2016).

J. Rusia, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma “RF Based Wireless Data Transmission between Two FPGAs”, International Conference on ICT in Business Industry Government (ICTBIG 2016).

Year 2015

P.Wakhradkar, A. Naugarhiya, and P. N. Kondekar, “Analysis of anisotropic 4h-sic sj drift layer,” in EESCO, Jan 2015, Visakhapatnam, India.

Year 2014

P. N. Kondekar and A. Naugarhiya, “Ac and transient analysis of sj vdmos,” in 11th ISETC, Nov 2014, Timisoara, Romania, Europe.

A. Naugarhiya and P. N. Kondekar, “Optimized process design flow for fabrication of superjunction vdmos for enhanced R_DSonA,” in 11th ISETC, Nov 2014, Timisoara, Romania, Europe.

Year 2013

A. Naugarhiya and P. N. Kondekar, “Electrical characteristics comparison between process and device structures of super junction VDMOS,” in CARE, Dec 2013, Jabalpur, India.

Book Chapter

A Ray, A Naugarhiya, GP Mishra “Impact of total ionizing dose effect on SOI-FinFET with spacer engineering” Device Circuit Co-Design Issues in FETs, pp.143-160.CRC PRESS (2023).

Conference Proceeding

Onika Parmar and Alok Naugarhiya, “Survey on charge plasma application in semiconductor devices”, presented at National and Computing (VCC 2017), organized by National Institute of technology, Raipur.

Vicky Butram and Alok Naugarhiya, “Cantilever based Piezoelectric Generator design using circular electrode”, presented at National and Computing (VCC 2017), organized by National Institute of technology, Raipur.

Namrata Gupta and Alok Naugarhiya, “Design and optimization of Microcantilever based sensor for chemicals”, presented at National and Computing (VCC 2017), organized by National Institute of technology, Raipur.

International Journal

Year 2024

1. A Ray, A Naugarhiya, GP Mishra “Improved post-radiation behavior of FinFET based CMOS with workfunction modulated gate”, Physica Scripta, Volume 99, Number 4, March 2024. DOI 10.1088/1402-4896/ad3386

2. Abhishek Ray, Alok Naugarhiya, Guru Prasad Mishra, “TID response of hybrid FinFET with modified gate dielectric”, Micro and Nanostructures, Volume 187, January 2024. DoI: https://doi.org/10.1016/j.micrna.2024.207759.

Year 2023

3. A Ray, A Naugarhiya, GP Mishra “Total ionizing dose effect of bulk and SOI P-FinFET with linear workfunction modulation technology” Microelectronics Journal Vol.137, pp. 105822(2023).

4. R Singh, A Naugarhiya, GP Mishra “Endurance behaviour of Z-shaped charge plasma Tunnel FET for biosensing application” Journal of Circuits, Systems and Computers (2023).

Year 2022

5. M Vaidya, A Naugarhiya, S Verma, GP Mishra “1.2 kV Stepped Oxide Trench Insulated Gate Bipolar Transistor with Low Loss for Fast Switching Application” ECS Journal of Solid State Science and Technology. Vol. 11, pp. 111008 (2022).

6. A Ray, A Naugarhiya, GP Mishra “ Analysis of total ionizing dose response of optimized fin geometry workfunction modulated SOI-FinFET ” journal of Microelectronics Reliability , Vol. 134, pp. 114549 (2022).

7. N Gupta, P Roy, A Naugarhiya “Design and investigation of split (n/n-) buffer layer semi-superjunction IGBT” Journal of Applied Physics A , Vol. 128 , pp. 376 (2022).

8. N Gupta, P Roy, O Parmar, A Naugarhiya “Plasma Enhancement Semi-Superjunction Trench IGBT with Higher Figure-of-Merit” Journal of Electronic Materials , Vol. 51 , pp. 2576-2585 (2022).

9. O Parmar, N Gupta, A Naugarhiya “Reduction in area‐specific on‐resistance with vertical stepped doped high‐k VDMOS” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields , Vol. 35 , pp. e2979 (2022).

10. V Butram, A Naugarhiya “Performance enhancement of piezoelectric mems energy harvester using split proof mass for powering ultralow power wireless sensor nodes” Arabian Journal for Science and Engineering , Vol. 47 , pp. 2755-2762 (2022).

11. M Vaidya, A Naugarhiya, S Verma, GP Mishra “Collector engineered bidirectional insulated gate bipolar transistor with low loss” Journal of IEEE Transactions on Electron Devices, Vol. 69 , pp. 1604-1607 (2022).

Year 2021

12. V Butram, A Mishra, A Naugarhiya “A lead-free spiral bimorph piezoelectric mems energy harvester for enhanced power density” IETE Technical Review , Vol. 38 , pp. 537-546 (2021).

13. O Parmar, A Naugarhiya “High temperature analysis of strained superjunction vertical single diffused MOSFET” International Journal of Modern Physics B , Vol. 35 , pp. 2150196 (2021).

14. M Vaidya, A Naugarhiya, S Verma, GP Mishra “A low-loss variable-doped trench-insulated gate bipolar transistor with reduced on-state voltage” Semiconductor Science and Technology , Vol. 36, pp. 075002 (2021).

15. S Agarwal, S Singh, BC Sahana, A Naugarhiya “Gaussian doped planar 4H-SiC junctionless field effect transistor for enhanced gate controllability” silicon , Vol. 13 , pp. 1609-1618 (2021).

16. N Gupta, A Naugarhiya “The design of a new heterogate superjunction insulated-gate bipolar transistor” Journal of Computational Electronics , Vol. 20 , pp. 883-891 (2021).

17. N Gupta, A Naugarhiya “1.4kV Planar Gate Superjunction IGBT with Stepped Doping Profile in Drift and Collector Region” Silicon, Vol.13, pp. 697-706 (2021). https://doi.org/10.1007/s12633-020-00456-8

18. Raj, A., Singh, S., Priyadarshani, K.N. et al. “Vertically Extended Drain Double Gate Si1−xGex Source Tunnel FET : Proposal & Investigation For Optimized Device Performance” Silicon 13, 2589–2604 (2021). https://doi.org/10.1007/s12633-020-00603-1

19. KN Priyadarshani, S Singh, A Naugarhiya “Dual metal double gate Ge-Pocket TFET (DMG-DG-Ge-Pocket TFET) with hetero dielectric: DC & analog performance projections” silicon , pp. 1-12 (2021).

20. KN Priyadarshani, S Singh, A Naugarhiya “RF & linearity distortion sensitivity analysis of DMG-DG-Ge pocket TFET with hetero dielectric” Microelectronics Journal , Vol. 108 , pp. 104973 (2021).

21. H Kumar, S Singh, KN Priyadarshani, J Ghosh “Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields , vol. 34 ,pp. e2812 (2021).

Year 2020

22. S Singh, S Singh, A Naugarhiya “Optimization of si-doped hfO2 ferroelectric material-based negative capacitance junctionless tfet: impact of temperature on rf/linearity performance” International Journal of Modern Physics B , Vol. 34 , pp. 2050242 (2020).

23. N. Gupta, S. Singh, & A. Naugarhiya, “An insulated gate bipolar transistor with three-layer poly gate for improved figure of merit” Journal of Materials Science: Materials in Electronics Vol. 31, 15513–15521 (2020).

24. Vicky Butram, Ashutosh Mishra & Alok Naugarhiya, “A Lead-Free Spiral Bimorph Piezoelectric MEMS Energy Harvester for Enhanced Power Density, IETE Technical Review, 2020. DOI: 10.1080/02564602.2020.1799876

25. M. Vaidya, A. Naugarhiya, S. Verma and G. P. Mishra, "Lateral Variation-Doped Insulated Gate Bipolar Transistor for Low On-State Voltage With Low Loss," in IEEE Electron Device Letters, vol. 41, no. 6, pp. 888-891, June 2020. Doi: 10.1109/LED.2020.2986941.

26. M Vaidya, A Naugarhiya, S Verma” Trench IGBT with stepped doped collector for low energy loss”, Semicond. Sci. Technol. 35, 2020. DOI 10.1088/1361-6641/ab6106

27. O Parmar, P Baghel, A Naugarhiya “Novel strained superjunction vertical single diffused MOSFET”, AEU - International Journal of Electronics and Communications, Volume 113, 2020. DOI: https://doi.org/10.1016/j.aeue.2019.152929.

Year 2019

28. P Nautiyal, A Naugarhiya, S Verma “An Assessment of Step Patterned Gate Oxide Superjunction Trench MOSFET for Potential Benefits”, J. Electron. Mater. 48, 8156–8162 (2019). https://doi.org/10.1007/s11664-019-07657-x.

29. P.Nautiyal, A. Naugarhiya, S.Verma, “Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications”, Semicond. Sci. Technol. 34 095016, 2019. DOI 10.1088/1361-6641/ab337f.

30. P.Nautiyal, A. Naugarhiya, S.Verma, “Strained superjunction U-MOSFET with insulating layer between alternate pillars”, Mater. Res. Express 6 046424, 2019. DOI 10.1088/2053-1591/aaff1d.

Year 2018

31. O.Parmar, A. Naugarhiya, “Incorporation of hafnium and platinum metal in vertical power MOSFETs”, J Comput Electron 17, 1241–1248 (2018). https://doi.org/10.1007/s10825-018-1193-x.

Year 2017

32. P.Nautiyal, A. Naugarhiya, S.Verma, “Novel Application of workfunction engineering in vertical superjunction devices” Superlattices and Microstructures, Volume 109, Pages 927-935, 2017. DOI: https://doi.org/10.1016/j.spmi.2017.06.024.

33. A. Naugarhiya” A Novel Charge-Protection SuperjunctionInsulator VDMOS”, International Journal of Electronics and Electrical Engineering Vol. 5, No. 3, June 2017.

34. A Naugarhiya, P Wakhradkar, PN Kondekar, GC Patil, RM Patrikar, “Analytical model for 4H-SiC superjunction drift layer with anisotropic properties for ultrahigh-voltage applications” Journal of Computational Electronics, vol.16, no.1, pp.190-201, 2017.

Year 2015

35. A Naugarhiya, PN Kondekar, “High permittivity material selection for design of optimum Hk VDMOS” Superlattices and Microstructures, vol. 83, pp.310-321, 2015.

36. A Naugarhiya, PN Kondekar, “Novel strained superjunction VDMOS” Superlattices and Microstructures, vol. 83, pp.310-321, 2015.

International Publications Conference

Year 2024

1. S. P. Behera, M. Vaidya and A. Naugarhiya, "Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application," 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), Kolkata, India, 2024, pp. 1-5, doi: 10.1109/VLSID60093.2024.00005.

Year 2023

2. A. Naugarhiya, C. Das and M. Vaidya, "Insulated Gate Bipolar Transistors with Deep Trench Technology for Low Loss Switching Application," 2023 International Conference on Modeling, Simulation & Intelligent Computing (MoSICom), Dubai, United Arab Emirates, 2023, pp. 317-321, doi: 10.1109/MoSICom59118.2023.10458719.

3. S. Gupta, D. K. Meda and A. Naugarhiya, "SEGR Analysis of SJ_IGBT with High-k Gate Dielectrics for Radiation Environment," 2023 World Conference on Communication & Computing (WCONF), RAIPUR, India, 2023, pp. 1-5, doi: 10.1109/WCONF58270.2023.10235100.

4. MH Manzoor, A Ray, A Naugarhiya “ Analysis of GaAs FinFET Based Biosensor with Under Gate Cavity” 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS) , pp. 1-6 (2023).

5. S Singh, S Ranjan, A Naugarhiya “SEGR and SEB Analysis of SJVDMOS using SiO 2/Si 3 N 4 as Gate Dielectric with Buffer layer” 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS) ,pp. 1-6 (2023).

Year 2022

6. A Ray, A Naugarhiya, GP Mishra “ Influence of total ionizing dose on LWM Bulk and SOI p-FinFET ” IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON). pp. 421-425 (2022).

7. M Vaidya, A Naugarhiya, S Verma, GP Mishra “1.2 kV Stepped Oxide Trench Insulated Gate Bipolar Transistor with Low Loss for Fast Switching Application” ECS Journal of Solid State Science and Technology. Vol. 11, pp. 111008 (2022).

8. V Butram, A Naugarhiya “Analysis of Split Proof Mass Pieozoelectric Cantilever based MEMS Energy Harvesting System using Ultra Low Power Rectifier Circuit” IEEE Region 10 Symposium (TENSYMP) , pp. 1-4 (2022).

9. S Yogi, A Naugarhiya “Performance Optimization of IGZO-Based Junctionless Thin Film Transistor for Low Power Application” Proceedings of Fifth International Conference on Inventive Material Science Applications: ICIMA , pp. 285-294 (2022).

10. J Pavuluri, SM Ranjan, A Naugarhiya “Analysis of Gate Oxides in LDMOS for Radiation Hardening Against SEGR” International Conference on Intelligent Controller and Computing for Smart Power (ICICCSP) , pp. 1-6 (2022).

11. M Vaidya, A Naugarhiya, S Verma, GP Mishra “Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application” International Symposium on VLSI Design and Test , pp. 53-64 (2022).

12. M Amjath, S Ranjan, A Naugarhiya “SEGR Analysis of Super Junction VDMOS using HfO 2 as Gate Dielectric” Second International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT) , pp. 1-5 (2022).

13. N Gupta, A Naugarhiya “Capacitive Analysis of Superjunction Vertical IGBT with Gate Engineering” First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT) , pp. 1-5 (2022).

14. V Butram, A Ray, A Naugarhiya, GPSC Mishra “A Novel Concept of Roof Top Tip Mass in Cantilever Based Energy Harvester for Wireless Sensor Node” Proceedings of the 2nd International Conference on Data Science, Machine Learning and Applications , pp. 1497-1504 (2022).

Year 2021

15. A Ray, A Naugarhiya, GP Mishra “Study of Gate Workfunction Modulated FinFET with Effect of TID” Modern Electronics Devices and Communication Systems: Select Proceedings of MEDCOM , pp. 253-259(2021).

16. P. Nautiyal, A. Naugarhiya and S. Verma, “Performance evaluation of superjunction UMOS with dual polysilicon gate." Materials Today: Proceedings 46 (2021): 4546-4552.

17. M. Vaidya, A. Naugarhiya and S. Verma, “Lateral variation doped wide bottom trench gate IGBT for reduced on-resistance with improved gate charge." Materials Today: Proceedings 46 (2021): 4587-4592.

18. N. Gupta and A. Naugarhiya. “1.4 kv superjunction igbt with variation doping profile for enhanced performance parameters." Materials Today: Proceedings 46 (2021): 4800-4806.

19. A Ray, A Naugarhiya, GP Mishra “Influence of SET effects in low-doped double gate MOSFETs” Materials Today: Proceedings , Vol. 43 , pp. 3867-3873 (2021).

20. R Verma, S Ranjan, A Naugarhiya “Analysis of Single Event Gate Rupture in Trench Gate SJ-VDMOS with SiO 2-Si 3 N 4 Dielectric Stacking” IEEE Region 10 Symposium (TENSYMP) , pp. 1-6 (2021).

21. O Parmar, P Nautiyal, A Naugarhiya “Capacitive Analysis of Strained Superjunction Vertical Single Diffused MOSFET” Devices for Integrated Circuit (DevIC) , pp. 139-142 (2021).

22. KN Priyadarshani, S Singh, A Naugarhiya “Impact of Temperature on DC and Analog/RF Performance for DM-DG-Ge Pocket TFET” Proceedings of International Conference on Communication and Artificial Intelligence: ICCAI 2020 , pp.135-141 (2021).

Year 2020

23. A Chunn, A Agrawal, A Naugarhiya, “An 8T TG-DTMOS Based Subthreshold SRAM Cell with Improved Write Ability and Access Times”, 2020 24th International Symposium on VLSI Design and Test (VDAT), 1-6.

24. S. Ranjan, S. Majumder and A. Naugarhiya, "SEGR Hardened Superjunction VDMOS with High-K Gate Dielectrics," 2020 International Conference on Power Electronics & IoT Applications in Renewable Energy and its Control (PARC), Mathura, Uttar Pradesh, India, 2020, pp. 272-275, doi: 10.1109/PARC49193.2020.236606.

Year 2019

25. P.Nautiyal, A. Agrawal, S. Kumari, H. Sahu, A. Naugarhiya and S. Verma, “"Electrical characteristic investigation of variation vertical doping superjunction UMOS." In 2019 IEEE 16th India Council International Conference (INDICON), pp. 1-4. IEEE, 2019.

26. M. Vaidya, A. Naugarhiya, S. Verma, “"Design and Analysis of Improved IGBT with Embedded p+ in N-Buffer Layer." In 2019 IEEE 16th India Council International Conference (INDICON), pp. 1-4. IEEE, 2019.

27. P.Shukla, A. Chunn, A.Naugarhiya, “A robust 13T single ended Schmitt trigger based SRAM cell." In 2019 5th International Conference on Signal Processing, Computing and Control (ISPCC), pp. 329-334. IEEE, 2019.

28. V.Butram, A.Naugarhiya, “An Efficient Design of Spiral Shaped MEMS Energy Harvester for Low Power Electronic Applications." In 2019 5th International Conference on Signal Processing, Computing and Control (ISPCC), pp. 335-338. IEEE, 2019.

29. Ajeet Singh Lowanshi, Onika Parmar, Anshul Gupta and Alok Naugarhiya “An Effective Charge Plasma based Semi-Superjunction MOSFET”, 2nd IEEE - International Conference on Systems Computation Automation and Networking “29th and 30th March 2019, ICSCAN 2019, Puducherry, India.

30. S. Hafizullah, Mahesh Vaidya, Shrish Verma, Alok Naugarhiya, " An efficient hardware architecture for route discovery in AODV for a sensor node." In 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON), pp. 70-74. IEEE, 2019.

31. Prashant Kumar Kushwaha, Payal Nautiyal, Anshul Gupta, Alok Naugarhiya, Shrish Verma, “An improved SJ UMOS with modified gate electrode to reduce gate charge." In 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON), pp. 81-84. IEEE, 2019.

32. Abhishek Ray, Vicky Butram, Namrata Gupta, Alok Naugarhiya, " "Non-Conventional Cantilever for Piezoelectric Energy Harvesting at Ultra Low Resonant Frequency." In 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON), pp. 90-93. IEEE, 2019.

Year 2018

33. Shaik Hafizullah, M. S. S. V Srikrishna Manideep, Vinay Sharma, PallabKumar Nath, Alok Naugarhiya, Shrish Verma, “An Efficient Hardware Implementation of Walsh Hadamard Transform for JPEG XR”, 15th Edition of the IEEE India Council International Conference (INDICON), 2018, organised by Amrita Vishwa Vidyapeetham, Coimbatore.

34. Namrata Gupta, Abhishek Ray, Alok Naugarhiya, Abhinav Gupta "Design and Optimization of MEMS Piezoelectric Cantilever for Vibration Energy Harvesting Application", in VCAS-2018 organised by MNNIT Allahabad.

35. Vicky Batrum, Alok Naugarhiya, “Non traditional proof mass arrangement in cantilever based pizeoelectric energy harvester” in ICCCS 2018 organized at Katmandu Nepal.

36. Onika Parmar and Alok Naugarhiya, “Application of workfunction engineering in lateral power devices” in International Conference on Advacnces in Electronics Computers and Communication (ICAECC 2018) organized by, REVA University, Bangalore, India.

37. M Vaidya, A. Naugarhiya, S. Verma, “High Speed Generic Voltage Level Shifter” Second International Conference on Electronics, Computers and Communications (ICAECC-2018), REVA University, Bangalore, India.

38. P. Nautiyal, A. Naugarhiya, S. Verma, “Charge Plasma Based VVD-SJ VDMOS Employing Reversed Doping Concentration” Second International Conference on Electronics, Computers and Communications (ICAECC-2018), REVA University, Bangalore, India.

39. P. Nautiyal, O. Parmar A. Naugarhiya, S. Verma, “Design and Performance Projection of Workfunction Engineered Variable Vertical Doped Superjuction Vertical Single Diffused MOS” International Conference on Electronics, Computing and Communication Technologies (IEEE CONECCT 2018), Bangalore, India.

40. Ankush Chunn, A. Naugarhiya, “Use of Open Source CAD Tools in VLSI Design Curriculum for Developing Countries” International Conference on Computing, Engineering and Information Technology (ICCEIT 2018) ,Bangkok, Thailand.

Year 2017

41. A. Sharma, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma, “VERILOG based simulation of ASK, FSK, PSK, QPSK digital modulation techniques”, International conference on IoT in Social, Mobile, Analytics and Cloud (I-SMAC 2017).

42. A. Chakradhari, S. Tamrakar, R. Basant, M. Vaidya, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder and S. Verma “Slotted CSMA/CA Simulation in Verilog”, International Workshop on Internet of Things and TV White Spaces (WIOT’ 2017).

43. A. Chaudhary, J. Rusia, K. Gourav, P. Tripathi, J. Pandey, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma, “Design and Simulation of Physical Layer Blocks of ZigBee Transmitter”, International conference on IoT in Social, Mobile, Analytics and Cloud (I-SMAC 2017).

Year 2016

44. J. Rusia, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma “Remote Temperature & Humidity sensing through ASK Modulation Technique”, International Conference on ICT in Business Industry Government (ICTBIG 2016).

45. J. Rusia, S. Majumdar, A. Naugarhiya, B. Acharya, S. Majumder, S. Verma “RF Based Wireless Data Transmission between Two FPGAs”, International Conference on ICT in Business Industry Government (ICTBIG 2016).

Year 2015

46. P.Wakhradkar, A. Naugarhiya, and P. N. Kondekar, “Analysis of anisotropic 4h-sic sj drift layer,” in EESCO, Jan 2015, Visakhapatnam, India.

Year 2014

47. P. N. Kondekar and A. Naugarhiya, “Ac and transient analysis of sj vdmos,” in 11th ISETC, Nov 2014, Timisoara, Romania, Europe.

48. A. Naugarhiya and P. N. Kondekar, “Optimized process design flow for fabrication of superjunction vdmos for enhanced R_DSonA,” in 11th ISETC, Nov 2014, Timisoara, Romania, Europe.

Year 2013

49. A. Naugarhiya and P. N. Kondekar, “Electrical characteristics comparison between process and device structures of super junction VDMOS,” in CARE, Dec 2013, Jabalpur, India.

Book Chapter

1. A Ray, A Naugarhiya, GP Mishra “Impact of total ionizing dose effect on SOI-FinFET with spacer engineering” Device Circuit Co-Design Issues in FETs, pp.143-160.CRC PRESS (2023).

Conference Proceeding

Onika Parmar and Alok Naugarhiya, “Survey on charge plasma application in semiconductor devices”, presented at National and Computing (VCC 2017), organized by National Institute of technology, Raipur.
Vicky Butram and Alok Naugarhiya, “Cantilever based Piezoelectric Generator design using circular electrode”, presented at National and Computing (VCC 2017), organized by National Institute of technology, Raipur.
Namrata Gupta and Alok Naugarhiya, “Design and optimization of Microcantilever based sensor for chemicals”, presented at National and Computing (VCC 2017), organized by National Institute of technology, Raipur.

Other Info.

1. Ph.D Thesis Supervision (Currently at NIT Raipur)

S. No.	Name	Area of Interest/ Title of Thesis	Name of other supervisor (If any)	Status
1	Payal Nautiyal (Joint-Supervisor)	Design and Analysis of Improved Superjunction Power MOSFETs with Optimized Parameters	Prof. (Dr) Shrish Verma	Awarded, October, 2020
2	Onika Parmar	Performance Parametric Optimization of Lateral and Vertical Power MOSFETs		Awarded, May, 2022
3	Mahesh Vaidaya (Joint-Supervisor)	Design and Analysis of Trench Superjunction Insulated Gate Bipolar Transistor: Limitations and Solutions	Prof. (Dr) Shrish Verma	Awarded, May, 2022
4	Vicky Butram	Design and Optimization of Ultra-Low Frequency Piezoelectric Micro-Cantilever for Energy Harvesting		Awarded, November, 2022
5	Namarta Gupta	Design and Analysis of Asymmetric Superjunction Insulated Gate Bipolar Transistor: Limitations and Solutions		Awarded, December, 2022
6	Sanjeev Ranjan (Supervisor)	Radiation Hardening in VDMOS	Dr. Saikat Majumder	Ongoing
7	Abhishek Ray (Supervisor)	Design of Radiation Hardened FinFET for Integrated Circuit Applications	Dr. GPSC Mishra	Awarded, April 2024
8	Upendra Soni	Design and Simulation of ISFET	Dr. Chitrakant Sahu	Ongoing
9	Y. Prasad,	Semiconductor Devices		Ongoing

2. M.Tech Thesis Supervision (Currently At NIT Raipur)

S.No.	Name	Area of Interest/Title of Thesis	Name of other supervisor (If any)	Year of Award
1.	Abhishek Ray	An optimal design of MEMS based Piezoelectric cantilever with tip mass for energy harvesting application		2019
2	Shaik Hafizullaha (Joint-Supervisor)	An efficient VLSI architecture of AODV protocol with prioritized contention axis clean for a sensor node	Prof. (Dr) Shrish Verma	2019
3.	Ajeet Singh Lowanshi (Joint-Supervisor)	Performance evolution of workfunction engineered and strained semisuperjunction vertical mosfet	Dr. Anshul Gupta	2019
4.	Prashant Kumar Kushwaha (Joint-Supervisor)	Performance evolution of strained poly silicon spacer supejunction UMOS	Dr. Anshul Gupta	2019
5	Prateek Bajaj	A surface potential-based threshold voltage and drain current model of core gate cylindrical Mosfet	Dr. GPSC Mishra	2020
6	Prannoy Roy	Deployment of plasma enhancement layer in semi superjunction IGBT		2020
7	Rohit Verma	Analysis of SEGR in Trench-VDMOS with High-k Dielectric		2021
8	Jyoti kumari	Parametric Analysis of Stepped Gate VDMOS		2021
9	Chumki Das	Insulated Gate Bipolar Transistor with Deep Trench Gate Engineering for Improved performance		2021
10	Shraddha Yogi	Performance Optimization of IGZO based Junctionless Thin Film Transistor for Low power application.		2022
11	Ragini Singh	Sensitivity analysis of Directly Modulated Z-shaped charge plasma TFET based label free biosensor		2022
12	MD Amjath	Radiation Hardening of Super junction VDMOS with Gate engineering technique		2022
13	Pavuluri Jayadev	Analysis of gate oxides in LDMOS for radiation hardening against SEGR		2022
14	Shivam Singh	Single Event Effects analysis of SJVDMOS		2023
15	Shriharsh Prasad Behera	Gate Engineering Impact on the Performance of Superjunction Insulated Gate Bipolar Transistor		2023
16	Md. Helal Manzoor	Design and Analysis of Under gate cavity GaAs FinFET based Biosensor		2023

3. B. Tech Project Supervised

S.No	Title of Project	Name of the student	Name of other supervisor (If any)	Year of Award
1	Design and simulation of physical layer blocks of zigbee transmitter using verilog	Janam Pandey Kumar Gaurav Parul Tripathi	Prof. (Dr) Shrish Verma	2016
2	Implementation of zigbee MAC layer CSMA-CA algorithm	Shreyash Tamrakar Rashmi Basant Vivek K. Singh Prakhar Goyal	Prof. (Dr) Shrish Verma	2016
3	Wireless temperature & humidity monitoring system through ASK modulation technique	Nilay Markam Sachin Paikera Prassana Kumar	Prof. (Dr) Shrish Verma	2016
4	Design and simulation of secured Transmitter for WSN	Akshay Sharma Amit Chakradhari Aaditya Chaudhary Jaydeep Rusia	Dr. Shubhankar Majumdar	2017
5	Impact of technology on the power amplifier performance	Chandan Kumar	Dr. Shubhankar Majumdar	2017
6	Thermal analysis of LSDMOS	Jagriti Sahu Neha Choudhary Sonalie Ahirwar	-	2017
7	Analysis of VDMOS and CPVDMOS	Atul Dewangan Deepraj Kant		2017
8	Application of workfunction engineering on strained superjunction vertical MOSFET	Prateek Baghel	Dr. Ankush Chunn	2018
9	Design and simulation of AES encryption/decryption algorithm in verilog	Dudekula Sadik Basha Janugani Thanuj Kumar	-	2018
10	An efficient hardware implementation of Walsh Hadamard transform for Jepg-XR Image compression	Vinay Sharma M. Srikrishna Maindeep	Dr. Pallab Kumar Nath	2018
11	Implementation of robust CMOS ternary content addressable memory using Cadence GPDK 45nm technology	Prakhar Shukla	Dr. Ankush Chunn	2019
12	Cordic based VLSI architecture for 16-QAM signal generator	Avvari Pavan Kumar		2019
13	Cordic based VLSI design of hann windowed sliding DFT	Pentakota Navin Kumar Ananthula Vijay Sai		2019
14	Workfunction engineered stepped oxide planer gate IGBT	Akansh Singh Sarita Singh Shraddha Tiwari		2019
15	Performance Parameter analysis of power Mosfets	Anjali Agrawaal Hema Sahu Shweeta Kumari		2019
16	128-Bit Datapath Optomised AES-128 Design for Speech Encryption and Decryption	Astha Agrawal	Rohit Shrivastava	2020
17	Hardware implementation of Unfolded Pipelined AES 128 bit decryption	Chintala Divya D Sharda	Rohit Shrivastava	2020
18	An 8T TG-DTMOS Based Subthreshold SRAM Cell with Improved Write Ability and Access Times	Akshay Agrawal	Dr. Ankush Chunn	2020
19	A Trench N-barrier layer controlled IGBT” is the bona-fide work done by Ankita Halder	Ankita Halder Monica Sindhu Chintada Shreyank Mishra		2020
20	Design and Analysis of High Power Density MEMS Energy Harvester	Mrigank Srivastava Mohit Kushwaha		2020
21	UV-C Disinfection Cell for Sanitization of Quotidian Things	Dampanaboyina Teja Nuka Tejeswararao P Vamsi Krishna		2021
22	Analysis of Vertically Diffused MOSFET	Arpit Gupta Hritika Singh Md Anaytullah Ansari		2021
23	Electrochemical Biosensor for Glucose Detection	Kadagala Atchum Naidu Bodiboyina Jagadeesh Pithani Pavan Kalyan		2021
24	Integration and Simulation of CSMA/CA and AES-128 in Verilog	Aditya Nahta Arnit Dey Ayam Mahajan		2022
25	Improvement of performance of Tunnel Field Effect Transistor & Design of Biosensor	Kalapala Sai Gowtham Madu Siva Tulasi Ram T. Abhinav		2022
26	Radiation Hardening in Superjunction VDMOS	Aman Tiwari Kairevu Vikramadithya Dharna Chandrakar		2022

4. Foreign Visits:

Timisoara, Romania, Europe for attending 11th ISETC at Politehnica University of Timisoara, Nov 2014.

Singapore for attending ACM's Int. Conf. on Graphics and Signal Processing at NTU, June 2017.

Hongkong for attending 25th International Conference on “Engineering & Technology, Computer, Basic & Applied Sciences” (ECBA- 2017). July 2017.

Bangkok, Thailand for attending 8th Int. Conf. on Computing, Engg. & IT (ICCEIT), March 2018

Kathmandu, Nepal for attending 3rd IEEE International Conference on Computing, Communication and Security at Institute of Engineering Tribhuvan University, October 2018.

5. Professional Membership:

Senior Member IEEE, IEI, IETE

6. Organization of Courses/Conferences

S.No.	Type of Program	Title of the Courses	Sponsored / Jointly Organized by	Date
1	STTP	VLISD-SoC and Micronano Technologies	TEQIP - II	26^th to 30^th Sep, 2016
2	Conference	National Conference on VLSI, Communication & Computing	TEQIP III	9^th Dec, 2017
3	FDP	Machine Learning and IoT	E&ICT Academy, PDPM IIITDMJ	11^th to 15^th March, 2019

7. Expert Talk/Key Note Speaker/ Session Chair:

Expert talk on “Recent Trends in VLSI Design” at Hitkarini College of Engineering and Technology on 01/09/2016.
Talk on the topic “How to write a research Paper” on 22^nd Dec 2016 at R.S.R Rungta College of Engineering and Technology.
Expert talk at Hitkarini College of Engineering and Technology from 26^th to 28^th Dec 2016.
Session Chair in International Conference on Innovations & Sustainable Development from 25^th -26^th March, 2017.
Key Note Speaker at AICON, 2016 organized by Electronics & Telecommunication Department of Chhatrapati Shivaji Institute of Technology.
Delivered Lecture in STTP organized by Department of IT, NIT Raipur on “Logic Building using C and MATLAB” at NIT Raipur in 2016.
Delivered Lecture in STTP organized by Department of Electrical Engineering NIT Raipur, on “Optimization Techniques and their implementation using MATLAB” at NIT Raipur in 2016.
Key Note Speaker at AICON, 2017 organized by Electronics & Telecommunication Department of Chhatrapati Shivaji Institute of Technology.
Expert Lecture at Smart Electronic Systems & IoT for Smart City 2017 organized at MNIT Jaipur.
Expert talk on “Vertical Power MOSFET’s” on 8^th -9^th Sept. 2017 at G.B. Pant Institute of Engineering and Technology, PAURI Garhwal.

8. Participated in Workshop

Participated in TEQIP II sponsored “Faculty Induction Programme” at NIT Raipur in Sept. 2016

Attended IEP at IIT Roorkee organized under SMDP C2SD project, MeitY, Govt. of India.

9. Academic Responsibility:

Design syllabus of M.Tech in “VLSI and Embedded System” at ETC, NIT Raipur.

Set up the Lab of VLSI & Microelectronics and is the lab in-charge from 2015 till date.

10. Courses Taught:

Digital Logic Design
VLSI and Microelectronics
Semiconductor Devices
Analog IC Design